Memory Accelerator Module (Mam); Introduction - Philips LPC2194 User Manual

Philips Semiconductors Preliminary User Manual
ARM-based Microcontroller LPC2119/2129/2194/2292/2294

5. MEMORY ACCELERATOR MODULE (MAM)

INTRODUCTION

Simply put, the Memory Accelerator Module (MAM) attempts to have the next ARM instruction that will be needed in its latches
in time to prevent CPU fetch stalls. The method used is to split the Flash memory into two banks, each capable of independent
accesses. Each of the two Flash banks has its own Prefetch Buffer and Branch Trail Buffer. The Branch Trail Buffers for the two
banks capture two 128-bit lines of Flash data when an Instruction Fetch is not satisfied by either the Prefetch buffer nor Branch
Trail buffer for its bank, and for which a prefetch has not been initiated. Each prefetch buffer captures one 128-bit line of
instructions from its Flash bank, at the conclusion of a prefetch cycle initiated speculatively by the MAM.
Each 128 bit value includes four 32-bit ARM instructions or eight 16-bit Thumb instructions. During sequential code execution,
typically one Flash bank contains or is fetching the current instruction and the entire Flash line that contains it. The other bank
contains or is prefetching the next sequential code line. After a code line delivers its last instruction, the bank that contained it
begins to fetch the next line in that bank.
Timing of Flash read operations is programmable and is described later in this section as well as in the System Control Block
section.
Branches and other program flow changes cause a break in the sequential flow of instruction fetches described above. When a
backward branch occurs, there is a distinct possibility that a loop is being executed. In this case the Branch Trail Buffers may
already contain the target instruction. If so, execution continues without the need for a Flash read cycle. For a forward branch,
there is also a chance that the new address is already contained in one of the Prefetch Buffers. If it is, the branch is again taken
with no delay.
When a branch outside the contents of the Branch Trail and Prefetch buffers is taken, one Flash Access cycle is needed to load
the Branch Trail buffers. Subsequently, there will typically be no further fetch delays until another such "Instruction Miss" occurs.
The Flash memory controller detects data accesses to the Flash memory and uses a separate buffer to store the results in a
manner similar to that used during code fetches. This allows faster access to data if it is accessed sequentially. A single line buffer
is provided for data accesses, as opposed to the two buffers per Flash bank that are provided for code accesses. There is no
prefetch function for data accesses.
Memory Accelerator Module Blocks
The Memory Accelerator Module is divided into several functional blocks:
• A Flash Address Latch for each bank. An Incrementer function is associated with the Bank 0 Flash Address latch.
• Two Flash Memory Banks.
• Instruction Latches, Data Latches, Address Comparison latches.
• Wait logic
Figure 18 shows a simplified block diagram of the Memory Accelerator Module data paths.
In the following descriptions, the term "fetch" applies to an explicit Flash read request from the ARM. "prefetch" is used to denote
a Flash read of instructions beyond the current processor fetch address.
Flash Memory Banks
There are two banks of Flash memory in order to allow two parallel accesses and eliminate delays for sequential accesses.
Memory Accelerator Module (MAM) 90 May 03, 2004