Table 116: Spi Status Register (S0Spsr - 0Xe0020004, S1Spsr - 0Xe0030004); Table 117: Spi Data Register (S0Spdr - 0Xe0020008, S1Spdr - 0Xe0030008); Table 118: Spi Clock Counter Register (S0Spccr - 0Xe002000C, S1Spccr - 0Xe003000C) - Philips LPC2194 User Manual

Philips Semiconductors
ARM-based Microcontroller
SPI Status Register (S0SPSR - 0xE0020004, S1SPSR - 0xE0030004)
The SPSR register controls the operation of the SPI as per the configuration bits setting.
Table 117: SPI Status Register (S0SPSR - 0xE0020004, S1SPSR - 0xE0030004)
SPSR Function
2:0 Reserved
3 ABRT
4 MODF
5 ROVR
6 WCOL
7 SPIF
SPI Data Register (S0SPDR - 0xE0020008, S1SPDR - 0xE0030008)
This bi-directional data register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI by writing
to this register. Data received by the SPI can be read from this register. When a master, a write to this register will start a SPI
data transfer. Writes to this register will be blocked from when a data transfer starts to when the SPIF status bit is set, and the
status register has not been read
Table 118: SPI Data Register (S0SPDR - 0xE0020008, S1SPDR - 0xE0030008)
SPDR Function
7:0 Data
SPI Clock Counter Register (S0SPCCR - 0xE002000C, S1SPCCR - 0xE003000C)
This register controls the frequency of a master's SCK. The register indicates the number of pclk cycles that make up an SPI
clock. The value of this register must always be an even number. As a result, bit 0 must always be 0. The value of the register
must also always be greater than or equal to 8. Violations of this can result in unpredictable behavior.
Table 119: SPI Clock Counter Register (S0SPCCR - 0xE002000C, S1SPCCR - 0xE003000C)
SPCCR Function
7:0 Counter
SPI Interface
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
When 1, this bit indicates that a slave abort has occurred. This
Slave abort.
bit is cleared by reading this register.
Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is
cleared by reading this register, then writing the SPI control register.
Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is
cleared by reading this register.
Write collision. When 1, this bit indicates that a write collision has occurred. This bit
is cleared by reading this register, then accessing the SPI data register.
SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is
complete. When a master, this bit is set at the end of the last cycle of the transfer.
When a slave, this bit is set on the last data sampling edge of the SCK. This bit is
cleared by first reading this register, then accessing the SPI data register.
Note: this is not the SPI interrupt flag. This flag is found in the SPINT registrer.
.
SPI Bi-directional data port
SPI Clock counter setting
LPC2119/2129/2194/2292/2294
Description
Description
Description
184
Preliminary User Manual
Reset
Value
NA
0
0
0
0
0
Reset
Value
0
Reset
Value
0
May 03, 2004