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Philips Semiconductors
ARM-based Microcontroller
Table 225: ETM Configuration
External Outputs
FIFOFULL Present
FIFO depth
Trace Packet Width
1. For details refer to ARM documentation "Embedded Trace Macrocell Specification (ARM IHI 0014E)".
PIN DESCRIPTION
Table 226: ETM Pin Description
Pin Name
Type
TRACECLK
Output
PIPESTAT[2:0]
Output
TRACESYNC
Output
TRACEPKT[3:0]
Output
EXTIN[0]
Input
RESET STATE OF MULTIPLEXED PINS
On the LPC2119/2129/2194/2292/2294, the ETM pin functions are multiplexed with P1.25-16. To have these pins come as a
Trace port, connect a weak bias resistor (4.7 k: ) between the P1.20/TRACESYNC pin and V
pins, do not connect a bias resistor to P1.20/TRACESYNC, and ensure that any external driver connected to P1.20/TRACESYNC
is either driving high, or is in high-impedance state, during Reset.
Embedded Trace Macrocell
Resource number/type
Trace Clock. The trace clock signal provides the clock for the trace port. PIPESTAT[2:0],
TRACESYNC, and TRACEPKT[3:0] signals are referenced to the rising edge of the trace
clock. This clock is not generated by the ETM block. It is to be derived from the system clock.
The clock should be balanced to provide sufficient hold time for the trace data signals. Half
rate clocking mode is supported. Trace data signals should be shifted by a clock phase from
TRACECLK. Refer to Figure 3.14 page 3.26 and figure 3.15 page 3.27 in "ETM7 Technical
Reference Manual" (ARM DDI 0158B), for example circuits that implements both half-rate-
clocking and shifting of the trace data with respect to the clock. For TRACECLK timings refer
to section 5.2 on page 5-13 in "Embedded Trace Macrocell Specification" (ARM IHI 0014E).
Pipe Line status. The pipeline status signals provide a cycle-by-cycle indication of what is
happening in the execution stage of the processor pipeline.
Trace synchronization. The trace sync signal is used to indicate the first packet of a group
of trace packets and is asserted HIGH only for the first packet of any branch address.
Trace Packet. The trace packet signals are used to output packaged address and data
information related to the pipeline status. All packets are eight bits in length. A packet is output
over two cycles. In the first cycle, Packet[3:0] is output and in the second cycle, Packet[7:4]
is output.
External Trigger Input.
LPC2119/2129/2194/2292/2294
Description
291
Preliminary User Manual
1
Small
0
Yes (Not wired)
10 bytes
4/8
. To have them come up as port
SS
May 03, 2004
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