Table 16: External Interrupt Wakeup Register (Extwake - 0Xe01Fc144); Table 17: External Interrupt Mode Register (Extmode - 0Xe01Fc148) - Philips LPC2194 User Manual

Philips Semiconductors
ARM-based Microcontroller

Table 16: External Interrupt Wakeup Register (EXTWAKE - 0xE01FC144)

EXTWAKE Function
0 EXTWAKE0
1 EXTWAKE1
2 EXTWAKE2
3 EXTWAKE3
7:4 Reserved
External Interrupt Mode Register (EXTMODE - 0xE01FC148)
The bits in this register select whether each EINT pin is level- or edge-sensitive. Only pins that are selected for the EINT function
(chapter Pin Connect Block on page 126) and enabled via the VICIntEnable register (chapter Vectored Interrupt Controller (VIC)
on page 96) can cause interrupts from the External Interrupt function (though of course pins selected for ) other functions may
cause interrupts from those functions).
Note: Software should only change a bit in this register when its interrupt is disabled in VICIntEnable, and should write
the corresponding 1 to EXTINT before re-enabling the interrupt, to clear the EXTINT bit that could be set by changing
the mode.

Table 17: External Interrupt Mode Register (EXTMODE - 0xE01FC148)

EXTMODE Function
0 EXTMODE0
1 EXTMODE1
2 EXTMODE2
3 EXTMODE3
7:4 Reserved
External Interrupt Polarity Register (EXTPOLAR - 0xE01FC14C)
In level-sensitive mode, the bits in this register select whether the corresponding pin is high- or low-active. In edge-sensitive
mode, they select whether the pin is rising- or falling-edge sensitive. Only pins that are selected for the EINT function (chapter
Pin Connect Block on page 126) and enabled in the VICIntEnable register (chapter Vectored Interrupt Controller (VIC) on page
96) can cause interrupts from the External Interrupt function (though of course pins selected for other functions may cause
interrupts from those functions).
Note: Software should only change a bit in this register when its interrupt is disabled in VICIntEnable, and should write
the corresponding 1 to EXTINT before re-enabling the interrupt, to clear the EXTINT bit that could be set by changing
the polarity.
System Control Block
When one, assertion of EINT0 will wake up the processor from Power Down mode.
When one, assertion of EINT1 will wake up the processor from Power Down mode.
When one, assertion of EINT2 will wake up the processor from Power Down mode.
When one, assertion of EINT3 will wake up the processor from Power Down mode.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
When 0, level-sensitivity is selected for EINT0. When 1, EINT0 is edge-sensitive.
When 0, level-sensitivity is selected for EINT1. When 1, EINT1 is edge-sensitive.
When 0, level-sensitivity is selected for EINT2. When 1, EINT2 is edge-sensitive.
When 0, level-sensitivity is selected for EINT3. When 1, EINT3 is edge-sensitive.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
LPC2119/2129/2194/2292/2294
Description
Description
71
Preliminary User Manual
Reset
Value
0
0
0
0
NA
Reset
Value
0
0
0
0
NA
May 03, 2004