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Philips Semiconductors
ARM-based Microcontroller
Table 55: Pin description for LPC2119/2129/2194
Pin
LQFP64
Type
Name
Pin #
44
O
40
O
36
O
32
O
28
I
I/O
24
64
O
60
I
56
I
52
I
20
I
TD1
10
O
RESET
57
I
XTAL1
62
I
XTAL2
61
O
6, 18, 25,
V
I
SS
42, 50
V
59
I
SSA
V
58
I
SSA_PLL
Pin Configuration
P1.21
PIPESTAT0 Pipeline Status, bit 0. Standard I/O port with internal pull-up.
P1.22
PIPESTAT1 Pipeline Status, bit 1. Standard I/O port with internal pull-up.
P1.23
PIPESTAT2 Pipeline Status, bit 2. Standard I/O port with internal pull-up.
P1.24
TRACECLK Trace Clock. Standard I/O port with internal pull-up.
P1.25
EXTIN0
External Trigger Input. Standard I/O with internal pull-up.
P1.26
RTCK
Returned Test Clock output. Extra signal added to the JTAG port.
Assists debugger synchronization when processor frequency varies.
Bi-directional pin with internal pullup. LOW on this pin while RESET is
LOW enables pins P1.31:26 to operate as a Debug port after reset.
Important:
LOW on pin P1.26 while RESET is LOW enables pins P1.31:26 to
operate as a Debug port after reset.
P1.27
TDO
Test Data out for JTAG interface.
P1.28
TDI
Test Data in for JTAG interface.
P1.29
TCK
Test Clock for JTAG interface.
P1.30
TMS
Test Mode Select for JTAG interface.
P1.31
TRST
Test Reset for JTAG interface.
TD1:CAN1 transmitter output. Pin is 5 V tolerant with built-in pull-up.
External Reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to
take on their default states, and processor execution to begin at address 0. TTL with hysteresis,
5V tolerant.
Input to the oscillator circuit and internal clock generator circuits.
Output from the oscillator amplifier.
Ground: 0V reference.
Analog Ground: 0V reference. This should nominally be the same voltage as V
isolated to minimize noise and error.
PLL Analog Ground: 0V reference. This should nominally be the same voltage as V
should be isolated to minimize noise and error.
LPC2119/2129/2194/2292/2294
Description
114
Preliminary User Manual
but should be
SS,
but
SS,
May 03, 2004
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