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Philips Semiconductors
ARM-based Microcontroller
VPB DIVIDER
The VPB Divider determines the relationship between the processor clock (cclk) and the clock used by peripheral devices (pclk).
The VPB Divider serves two purposes. The first is to provides peripherals with desired pclk via VPB bus so that they can operate
at the speed chosen for the ARM processor. In order to achieve this, the VPB bus may be slowed down to one half or one fourth
of the processor clock rate. Because the VPB bus must work properly at power up (and its timing cannot be altered if it does not
work since the VPB divider control registers reside on the VPB bus), the default condition at reset is for the VPB bus to run at
one quarter speed. The second purpose of the VPB Divider is to allow power savings when an application does not require any
peripherals to run at the full processor rate.
The connection of the VPB Divider relative to the oscillator and the processor clock is shown in Figure 17. Because the VPB
Divider is connected to the PLL output, the PLL remains active (if it was running) during Idle mode.
VPBDIV Register (VPBDIV - 0xE01FC100)
The VPB Divider register contains two bits, allowing three divider values, as shown in Table 34.
Table 33: VPBDIV Register Map
Address
Name
0xE01FC100
VPBDIV
Table 34: VPB Divider Register (VPBDIV - 0xE01FC100)
VPBDIV
Function
1:0
VPBDIV
3:2
Reserved
5:4
XCLKDIV
7:6
Reserved
System Control Block
Controls the rate of the VPB clock in relation to the processor clock.
The rate of the VPB clock is as follows:
0 0: VPB bus clock is one fourth of the processor clock.
0 1: VPB bus clock is the same as the processor clock.
1 0: VPB bus clock is one half of the processor clock.
1 1: Reserved. If this value is written to the VPBDIV register, it has no effect (the
previous setting is retained).
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
In the LPC2292/2294 (parts in 144 packages) only, these bits control the clock that can
be driven onto the A23/XCLK pin. They have the same encoding as the VPBDIV bits
above. A bit in the PINSEL2 register (Pin Connect Block on page 126) controls whether
the pin carries A23 or the clock selected by this field.
Note: If this field and VPBDIV have the same value, the same clock is used on the
VPB and XCLK. (This might be useful for external logic dealing with the VPB
peripherals).
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
LPC2119/2129/2194/2292/2294
Description
Description
86
Preliminary User Manual
Access
R/W
Reset
Value
0
0
0
0
May 03, 2004
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