Table 48: Irq Status Register (Vicfiqstatus - 0Xfffff004, Read-Only); Table 49: Vector Control Registers (Vicvectcntl0-15 - 0Xfffff200-23C, Read/Write); Table 50: Vector Address Registers (Vicvectaddr0-15 - 0Xfffff100-13C, Read/Write); Table 51: Default Vector Address Register (Vicdefvectaddr - 0Xfffff034, Read/Write) - Philips LPC2194 User Manual

Philips Semiconductors
ARM-based Microcontroller
FIQ Status Register (VICFIQStatus - 0xFFFFF004, Read Only)
This register reads out the state of those interrupt requests that are enabled and classified as FIQ. If more than one request is
classified as FIQ, the FIQ service routine can read this register to see which request(s) is (are) active.

Table 48: IRQ Status Register (VICFIQStatus - 0xFFFFF004, Read-Only)

VICFIQStatus
31:0 1: the interrupt request with this bit number is enabled, classified as FIQ, and asserted.
Vector Control Registers 0-15 (VICVectCntl0-15 - 0xFFFFF200-23C, Read/Write)
Each of these registers controls one of the 16 vectored IRQ slots. Slot 0 has the highest priority and slot 15 the lowest. Note that
disabling a vectored IRQ slot in one of the VICVectCntl registers does not disable the interrupt itself, the interrupt is simply
changed to the non-vectored form.

Table 49: Vector Control Registers (VICVectCntl0-15 - 0xFFFFF200-23C, Read/Write)

VICVectCntl0-15
1: this vectored IRQ slot is enabled, and can produce a unique ISR address when its
5
assigned interrupt request or software interrupt is enabled, classified as IRQ, and asserted.
The number of the interrupt request or software interrupt assigned to this vectored IRQ slot.
As a matter of good programming practice, software should not assign the same interrupt
4:0 number to more than one enabled vectored IRQ slot. But if this does occur, the lower-
numbered slot will be used when the interrupt request or software interrupt is enabled,
classified as IRQ, and asserted.
Vector Address Registers 0-15 (VICVectAddr0-15 - 0xFFFFF100-13C, Read/Write)
These registers hold the addresses of the Interrupt Service routines (ISRs) for the 16 vectored IRQ slots.

Table 50: Vector Address Registers (VICVectAddr0-15 - 0xFFFFF100-13C, Read/Write)

VICVectAddr0-15
When one or more interrupt request or software interrupt is (are) enabled, classified as IRQ,
asserted, and assigned to an enabled vectored IRQ slot, the value from this register for the
31:0
highest-priority such slot will be provided when the IRQ service routine reads the Vector
Address register (VICVectAddr).
Default Vector Address Register (VICDefVectAddr - 0xFFFFF034, Read/Write)
This register holds the address of the Interrupt Service routine (ISR) for non-vectored IRQs.

Table 51: Default Vector Address Register (VICDefVectAddr - 0xFFFFF034, Read/Write)

VICDefVectAddr
When an IRQ service routine reads the Vector Address register (VICVectAddr), and no IRQ
31:0
slot responds as described above, this address is returned.
Vectored Interrupt Controller (VIC)
LPC2119/2129/2194/2292/2294
Function
Function
Function
Function
101
Preliminary User Manual
Reset Value
0
Reset Value
0
0
Reset Value
0
Reset Value
0
May 03, 2004