Prefetch Abort And Data Abort Exceptions - Philips LPC2194 User Manual

Philips Semiconductors
ARM-based Microcontroller

PREFETCH ABORT AND DATA ABORT EXCEPTIONS

The LPC2119/2129/2194/2292/2294 generates the appropriate bus cycle abort exception if an access is attempted for an
address that is in a reserved or unassigned address region. The regions are:
• Areas of the memory map that are not implemented for a specific ARM derivative. For the LPC2119/2129/2194/2292/2294,
this is:
- Address space between On-Chip Non-Volatile Memory and On-Chip SRAM, labelled "Reserved for On-Chip Memory" in
Figure 2 and Figure 6. For 128 kB Flash device, this is memory address range from 0x0002 0000 to 0x3FFF FFFF, while for
256 kB Flash device this range is from 0x0004 0000 to 0x3FFF FFFF.
- Address space between On-Chip Static RAM and External Memory. Labelled "Reserved for On-Chip Memory" in Figure 2.
This is an address range from 0x4000 3FFF to 0x7FFF DFFF.
- External Memory other than that provided by the EMC in the 144-pin package.
- Reserved regions of the AHB and VPB spaces. See Figure 3.
• Unassigned AHB peripheral spaces. See Figure 4.
• Unassigned VPB peripheral spaces. See Figure 5.
For these areas, both attempted data access and instruction fetch generate an exception. In addition, a Prefetch Abort exception
is generated for any instruction fetch that maps to an AHB or VPB peripheral address.
Within the address space of an existing VPB peripheral, a data abort exception is not generated in response to an access to an
undefined address. Address decoding within each peripheral is limited to that needed to distinguish defined registers within the
peripheral itself. For example, an access to address 0xE000D000 (an undefined address within the UART0 space) may result in
an access to the register defined at address 0xE000C000. Details of such address aliasing within a peripheral space are not
defined in the LPC2119/2129/2194/2292/2294 documentation and are not a supported feature.
Note that the ARM core stores the Prefetch Abort flag along with the associated instruction (which will be meaningless) in the
pipeline and processes the abort only if an attempt is made to execute the instruction fetched from the illegal address. This
prevents accidental aborts that could be caused by prefetches that occur when code is executed very near a memory boundary.
LPC2119/2129/2292/2294 Memory Addressing
LPC2119/2129/2194/2292/2294
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Preliminary User Manual
May 03, 2004