Figure 33: Spi Data Transfer Format (Cpha = 0 And Cpha = 1); Table 112: Spi Data To Clock Phase Relationship - Philips LPC2194 User Manual

Philips Semiconductors
ARM-based Microcontroller
SCK (CPOL = 0)
SCK (CPOL = 1)
CPHA = 0
Cycle # CPHA = 0
MOSI (CPHA = 0)
MISO (CPHA = 0)
CPHA = 1
Cycle # CPHA = 1
MOSI (CPHA = 1)
MISO (CPHA = 1)
The data and clock phase relationships are summarized in Table 113. This table summarizes the following for each setting of
CPOL and CPHA.
• When the first data bit is driven.
• When all other data bits are driven.
• When data is sampled.
Table 113: SPI Data To Clock Phase Relationship
CPOL And CPHA Settings
CPOL = 0, CPHA = 0
CPOL = 0, CPHA = 1
CPOL = 1, CPHA = 0
CPOL = 1, CPHA = 1
The definition of when an 8 bit transfer starts and stops is dependent on whether a device is a master or a slave, and the setting
of the CPHA variable.
SPI Interface
SSEL
1 2
Bit 1 Bit 2
Bit 1 Bit 2
1
Bit 1
Bit 1

Figure 33: SPI Data Transfer Format (CPHA = 0 and CPHA = 1)

First Data Driven
Prior to first SCK rising edge
First SCK rising edge
Prior to first SCK falling edge
First SCK falling edge
3 4 5
Bit 3 Bit 4 Bit 5
Bit 3 Bit 4 Bit 5 Bit 6
2 3 4 5
Bit 2 Bit 3 Bit 4 Bit 5
Bit 2 Bit 3 Bit 4 Bit 5
Other Data Driven
SCK falling edge
SCK rising edge
SCK rising edge
SCK falling edge
179
LPC2119/2129/2194/2292/2294
6 7 8
Bit 6 Bit 7 Bit 8
Bit 7 Bit 8
6 7 8
Bit 6 Bit 7 Bit 8
Bit 6 Bit 7 Bit 8
Data Sampled
SCK rising edge
SCK falling edge
SCK falling edge
SCK rising edge
Preliminary User Manual
May 03, 2004