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Philips Semiconductors
ARM-based Microcontroller
REGISTER DESCRIPTION
The SPI contains 5 registers as shown in Table 115. All registers are byte, half word and word accessible.
Table 115: SPI Register Map
Generic
Name
SPI Control Register. This register controls the operation of
SPCR
the SPI.
SPSR
SPI Status Register. This register shows the status of the SPI.
SPI Data Register. This bi-directional register provides the
transmit and receive data for the SPI. Transmit data is
SPDR
provided to the SPI by writing to this register. Data received by
the SPI can be read from this register.
SPI Clock Counter Register. This register controls the
SPCCR
frequency of a master's SCK.
SPI Interrupt Flag. This register contains the interrupt flag for
SPINT
the SPI interface.
*Reset Value refers to the data stored in used bits only. It does not include reserved bits content.
SPI Control Register (S0SPCR - 0xE0020000, S1SPCR - 0xE0030000)
The SPCR register controls the operation of the SPI as per the configuration bits setting.
Table 116: SPI Control Register (S0SPCR - 0xE0020000, S1SPCR - 0xE0030000)
SPCR
Function
2:0
Reserved
3
CPHA
4
CPOL
5
MSTR
6
LSBF
7
SPIE
SPI Interface
Description
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
Clock phase control determines the relationship between the data and the clock on
SPI transfers, and controls when a slave transfer is defined as starting and ending.
When 1, data is sampled on the second clock edge of the SCK. A transfer starts with
the first clock edge, and ends with the last sampling edge when the SSEL signal is
active.
When 0, data is sampled on the first clock edge of SCK. A transfer starts and ends
with activation and deactivation of the SSEL signal.
Clock polarity control. When 1, SCK is active low. When 0, SCK is active high.
Master mode select. When 1, the SPI operates in Master mode. When 0, the SPI
operates in Slave mode.
which direction each byte is shifted when transferred.
LSB First controls
1, SPI data is transferred LSB (bit 0) first. When 0, SPI data is transferred MSB (bit
7) first.
Serial peripheral interrupt enable. When 1, a hardware interrupt is generated each
time the SPIF or MODF bits are activated. When 0, SPI interrupts are inhibited.
LPC2119/2129/2194/2292/2294
Reset
Access
Value*
Read/
0
Write
Read
0
Only
Read/
0
Write
Read/
0
Write
Read/
0
Write
Description
183
Preliminary User Manual
SPI0
SPI1
Address &
Address &
Name
Name
0xE0020000
0xE0030000
S0SPCR
S1SPCR
0xE0020004
0xE0030004
S0SPSR
S1SPSR
0xE0020008
0xE0030008
S0SPDR
S1SPDR
0xE002000C
0xE003000C
S0SPCCR
S1SPCCR
0xE002001C
0xE003001C
S0SPINT
S1SPINT
Reset
Value
NA
0
0
0
When
0
0
May 03, 2004
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