Table 8: Bank Configuration Registers 0-3 (Bcfg0-3 - 0Xffe00000-0C); Table 9: Default Memory Widths At Reset - Philips LPC2194 User Manual

Philips Semiconductors
ARM-based Microcontroller
Bank Configuration Registers 0 - 3 (BCFG0-3 - 0xFFE00000-0C)
BCFG0-3 Name Function
This field controls the minimum number of "idle" CCLK cycles that the EMC maintains
between read and write accesses in this bank, and between an access in another bank
3:0 IDCY
and an access in this bank, to avoid bus contention between devices. The number of
idle CCLK cycles between such accesses is the value in this field plus 1.
Reserved, user software should not write ones to reserved bits. The value read from a
4 Reserved
reserved bit is not defined.
This field controls the length of read accesses, except for subsequent reads from a
9:5 WST1 burst ROM. The length of such read accesses, in CCLK cycles, is the value in this field
plus 3.
This bit should be 0 for banks composed of byte-wide or non-byte-partitioned devices,
so that the EMC drives the BLS3:0 lines High during read accesses. This bit should be
10 RBLE
1 for banks composed of 16-bit and 32-bit wide devices that include byte select inputs,
so that the EMC drives the BLS3:0 lines Low during read accesses.
For SRAM banks, this field controls the length of write accesses, which consist of:
• one CCLK cycle of address setup with CS, BLS, and WE high,
• (this value plus 1) CCLK cycles with address valid and CS, BLS, and WE low, and
15:11 WST2
• one CCLK cycle with address valid, CS low, BLS and WE high.
For burst ROM banks, this field controls the length of subsequent accesses, which are
(this value plus 1) CCLK cycles long.
Reserved, user software should not write ones to reserved bits. The value read from a
16:23 Reserved
reserved bit is not defined.
The only known case in which this bit is set is if the EMC detects an AMBA request for
24 BUSERR
more than 32 bits of data. The ARM7TDMI-S will not make such a request.
This bit is set if software attempts to write to a bank that has the WP bit 1. Write a 1 to
25 WPERR
this bit to clear it.
26 WP A 1 in this bit write-protects the bank.
27 BM A 1 in this bit identifies a burst-ROM bank.
This field controls the width of the data bus for this bank:
29:28 MW
00=8 bit, 01=16 bit, 10=32 bit, 11=reserved
31:30 AT Always write 00 to this field.

Table 8: Bank Configuration Registers 0-3 (BCFG0-3 - 0xFFE00000-0C)

The table below shows the state of BCFG0[29:28] after the Boot Loader has run. The hardware reset state of these bits is 10.
Bank BOOT[1:0] during Reset BCFG[29:28] Reset value Memory Width
0 LL
0 LH
0 HL
1 XX
2 XX
3 XX

Table 9: Default memory widths at Reset

External Memory Controller (EMC)
00 8 bits
01 16 bits
10 32 bits
10 32 bits
01 16 bits
00 8 bits
58
Preliminary User Manual
LPC2119/2129/2194/2292/2294
.
Reset Value
1111
NA
11111
0
11111
NA
0
0
0
0
see Table 9
00
May 03, 2004