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Philips Semiconductors
Volume 1
the Prefetch and Branch Trail Buffer is taken, a stall of several clocks is needed to load the
Branch Trail buffer. Subsequently, there will typically be no further instructionfetch delays
until a new and different branch occurs.
4.3 MAM blocks
The Memory Accelerator Module is divided into several functional blocks:
Figure 13
In the following descriptions, the term "fetch" applies to an explicit Flash read request from
the ARM. "Pre-fetch" is used to denote a Flash read of instructions beyond the current
processor fetch address.
4.3.1 Flash memory bank
There is one bank of Flash memory with the LPC2131/2/4/6/8 MAM.
Flash programming operations are not controlled by the MAM, but are handled as a
separate function. A "boot block" sector contains Flash programming algorithms that may
be called as part of the application program, and a loader that may be run to allow serial
programming of the Flash memory.
User manual
•
A Flash Address Latch and an incrementor function to form prefetch addresses
•
A 128-bit Prefetch Buffer and an associated Address latch and comparator
•
A 128-bit Branch Trail Buffer and an associated Address latch and comparator
•
A 128-bit Data Buffer and an associated Address latch and comparator
•
Control logic
•
Wait logic
shows a simplified block diagram of the Memory Accelerator Module data paths.
ARM Local Bus
Fig 13. Simplified block diagram of the Memory Accelerator Module (MAM)
Rev. 01 — 24 June 2005
Memory Address
BUS
INTERFACE
Memory Data
UM10120
Chapter 4: MAM Module
Flash Memory
Bank
BUFFERS
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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