Table of Contents
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Volume 1
8.4.2
GPIO Output Set register 0 and 1 (IO0SET -
0xE002 8004 and IO1SET - 0xE002 8014) . . 81
8.4.3
GPIO Output Clear register 0 and 1 (IO0CLR -
0xE002 800C and IO1CLR - 0xE002 801C). . 81
8.4.4
GPIO Direction Register 0 and 1 (IO0DIR -
0xE002 8008 and IO1DIR - 0xE002 8018) . . . 81
Chapter 9: Universal Asynchronous Receiver/Transmitter 0 (UART0)
9.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
9.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 84
9.3
Register description . . . . . . . . . . . . . . . . . . . . 84
9.3.1
UART0 Receiver Buffer Register (U0RBR -
0xE000 C000, when DLAB = 0, Read Only). . 86
9.3.2
UART0 Transmit Holding Register (U0THR -
0xE000 C000, when DLAB = 0, Write Only). . 86
9.3.3
UART0 Divisor Latch Registers 0 and 1 (U0DLL -
0xE000 C000 and U0DLM - 0xE000 C004, when
DLAB = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
9.3.4
UART0 Baud-rate calculation . . . . . . . . . . . . . 87
9.3.5
UART0 Interrupt Enable Register (U0IER -
0xE000 C004, when DLAB = 0) . . . . . . . . . . . 87
Chapter 10: Universal Asynchronous Receiver/Transmitter 1 (UART1)
10.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
10.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 95
10.3
Register description . . . . . . . . . . . . . . . . . . . . 96
10.3.1
UART1 Receiver Buffer Register (U1RBR -
0xE001 0000, when DLAB = 0 Read Only) . . 98
10.3.2
UART1 Transmitter Holding Register (U1THR -
0xE001 0000, when DLAB = 0 Write Only) . . 98
10.3.3
UART1 Divisor Latch Registers 0 and 1 (U1DLL -
0xE001 0000 and U1DLM - 0xE001 0004, when
DLAB = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
10.3.4
UART1 Baud-rate calculation . . . . . . . . . . . . . 99
10.3.5
UART1 Interrupt Enable Register (U1IER -
0xE001 0004, when DLAB = 0) . . . . . . . . . . . 99
10.3.6
UART1 Interrupt Identification Register (U1IIR -
0xE001 0008, Read Only) . . . . . . . . . . . . . . 100
2
Chapter 11: I
C interfaces I
11.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 110
2
11.5
I
C operating modes . . . . . . . . . . . . . . . . . . . 110
11.5.1
Master Transmitter mode . . . . . . . . . . . . . . . 110
User manual
2
2
C0 and I
C1
Rev. 01 — 24 June 2005
Chapter 24: Supplementary information
8.5
GPIO usage notes . . . . . . . . . . . . . . . . . . . . . . 82
8.5.1
Example 1: sequential accesses to IOSET and
IOCLR affecting the same GPIO pin/bit . . . . . 82
8.5.2
Example 2: immediate output of 0s and 1s on a
GPIO port. . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
8.5.3
Writing to IOSET/IOCLR .vs. IOPIN. . . . . . . . 83
9.3.6
UART0 Interrupt Identification Register (U0IIR -
0xE000 C008, Read Only) . . . . . . . . . . . . . . . 88
9.3.7
UART0 FIFO Control Register (U0FCR -
0xE000 C008) . . . . . . . . . . . . . . . . . . . . . . . . 90
9.3.8
UART0 Line Control Register (U0LCR -
0xE000 C00C) . . . . . . . . . . . . . . . . . . . . . . . . 90
9.3.9
UART0 Line Status Register (U0LSR -
0xE000 C014, Read Only) . . . . . . . . . . . . . . . 91
9.3.10
UART0 Scratch pad register (U0SCR -
0xE000 C01C) . . . . . . . . . . . . . . . . . . . . . . . . 92
9.3.11
UART0 Transmit Enable Register (U0TER -
0xE000 C030) . . . . . . . . . . . . . . . . . . . . . . . . 93
9.4
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
10.3.7
UART1 FIFO Control Register (U1FCR -
0xE001 0008). . . . . . . . . . . . . . . . . . . . . . . . 102
10.3.8
UART1 Line Control Register (U1LCR -
0xE001 000C) . . . . . . . . . . . . . . . . . . . . . . . 103
10.3.9
UART1 Modem Control Register (U1MCR -
0xE001 0010), LPC2134/6/8 only . . . . . . . . 104
10.3.10
UART1 Line Status Register (U1LSR -
0xE001 0014, Read Only) . . . . . . . . . . . . . . 104
10.3.11
UART1 Modem Status Register (U1MSR -
0xE001 0018), LPC2134/6/8 only . . . . . . . . 106
10.3.12
UART1 Scratch pad register (U1SCR -
0xE001 001C) . . . . . . . . . . . . . . . . . . . . . . . 106
10.3.13
UART1 Transmit Enable Register (U1TER -
0xE001 0030). . . . . . . . . . . . . . . . . . . . . . . . 106
10.4
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.5.2
Master Receiver mode . . . . . . . . . . . . . . . . . 111
11.5.3
Slave Receiver mode . . . . . . . . . . . . . . . . . . 112
11.5.4
Slave Transmitter mode . . . . . . . . . . . . . . . . 113
2
11.6
I
C Implementation and operation. . . . . . . . 114
11.6.1
Input filters and output stages . . . . . . . . . . . 114
11.6.2
Address Register, I2ADDR . . . . . . . . . . . . . 116
11.6.3
Comparator . . . . . . . . . . . . . . . . . . . . . . . . . 116
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
UM10120
continued >>
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