Philips LPC213 Series User Manual page 46

Philips Semiconductors
Volume 1
Table 30:
Name
MAMCR Memory Accelerator Module Control Register.
MAMTIM Memory Accelerator Module Timing control.
[1]
4.7 MAM Control Register (MAMCR - 0xE01F C000)
Two configuration bits select the three MAM operating modes, as shown in
Following Reset, MAM functions are disabled. Changing the MAM operating mode causes
the MAM to invalidate all of the holding latches, resulting in new reads of Flash information
as required.
Table 31:
Bit
1:0
7:2
4.8 MAM Timing register (MAMTIM - 0xE01F C004)
The MAM Timing register determines how many CCLK cycles are used to access the
Flash memory. This allows tuning MAM timing to match the processor operating
frequency. Flash access times from 1 clock to 7 clocks are possible. Single clock Flash
accesses would essentially remove the MAM from timing calculations. In this case the
MAM mode may be selected to optimize power usage.
Table 32:
Bit
2:0
User manual
Summary of MAM registers
Description
Determines the MAM functional mode, that is, to
what extent the MAM performance enhancements
are enabled. See Table
Determines the number of clocks used for Flash
memory fetches (1 to 7 processor clocks).
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
MAM Control Register (MAMCR - address 0xE01F C000) bit description
Symbol Value Description
MAM_mode 00
_control
01
10
11
- -
MAM Timing register (MAMTIM - address 0xE01F C004) bit description
Symbol Value Description
MAM_fetch_ 000 0 - Reserved.
cycle_timing
001 1 - MAM fetch cycles are 1 processor clock (CCLK) in
duration
010 2 - MAM fetch cycles are 2 CCLKs in duration
011 3 - MAM fetch cycles are 3 CCLKs in duration
100 4 - MAM fetch cycles are 4 CCLKs in duration
101 5 - MAM fetch cycles are 5 CCLKs in duration
Rev. 01 — 24 June 2005
31.
MAM functions disabled
MAM functions partially enabled
MAM functions fully enabled
Reserved. Not to be used in the application.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
UM10120
Chapter 4: MAM Module
Access Reset Address
[1]
value
R/W 0x0 0xE01F C000
R/W 0x07 0xE01F C004
Table
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
31.
Reset
value
0
NA
Reset
value
07
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