Philips LPC213 Series User Manual page 168

Philips Semiconductors
Volume 1
Important: the SSPCPSR value must be properly initialized or the SSP controller will not
be able to transmit data corectly. In case of an SSP operating in the master mode, the
CPSDVSR
13.4.6 SSP Interrupt Mask Set/Clear register (SSPIMSC - 0xE006 8014)
This register controls whether each of the four possible interrupt conditions in the SSP
controller are enabled. Note that ARM uses the word "masked" in the opposite sense from
classic computer terminology, in which "masked" meant "disabled". ARM uses the word
"masked" to mean "enabled". To avoid confusion we will not use the word "masked".
Table 140: SSP Interrupt Mask Set/Clear register (SSPIMSC - address 0xE006 8014) bit
Bit
0
1
2
3
7:4
13.4.7 SSP Raw Interrupt Status register (SSPRIS - 0xE006 8018)
This read-only register contains a 1 for each interrupt condition that is asserted,
regardless of whether or not the interrupt is enabled in the SSPIMSC.
Table 141: SSP Raw Interrupt Status register (SSPRIS - address 0xE006 8018) bit description
Bit
0
1
2
3
7:4
User manual
= 2, while in case of the slave mode CPSDVSR
min
description
Symbol Description
RORIM Software should set this bit to enable interrupt when a Receive
Overrun occurs, that is, when the Rx FIFO is full and another
frame is completely received. The ARM spec implies that the
preceding frame data is overwritten by the new frame data
when this occurs.
RTIM Software should set this bit to enable interrupt when a Receive
Timeout condition occurs. A Receive Timeout occurs when the
Rx FIFO is not empty, and no new data has been received, nor
has data been read from the FIFO, for 32 bit times.
RXIM Software should set this bit to enable interrupt when the Rx
FIFO is at least half full.
TXIM Software should set this bit to enable interrupt when the Tx
FIFO is at least half empty.
- Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Symbol Description
RORRIS This bit is 1 if another frame was completely received while the
RxFIFO was full. The ARM spec implies that the preceding
frame data is overwritten by the new frame data when this
occurs.
RTRIS This bit is 1 if when there is a Receive Timeout condition. Note
that a Receive Timeout can be negated if further data is
received.
RXRIS This bit is 1 if the Rx FIFO is at least half full.
TXRIS This bit is 1 if the Tx FIFO is at least half empty.
- Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 01 — 24 June 2005
UM10120
Chapter 13: SSP
= 12.
min
Reset value
0
0
0
0
NA
Reset value
0
0
0
1
NA
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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