Philips LPC213 Series User Manual page 196

Philips Semiconductors
Volume 1
16.4.2 A/D Data Register (AD0DR - 0xE003 4004 and AD1DR - 0xE006 0004)
Table 164: A/D Data Register (AD0DR - address 0xE003 4004 and AD1DR - address 0xE006 0004) bit description
Bit Symbol
5:0 -
15:6 V/V
REF
23:16 -
26:24 CHN
29:27 -
30 OVERUN
31 DONE
16.4.3 A/D Global Start Register (ADGSR - 0xE003 4008)
Software can write this register to simultaneously initiate conversions on both A/D
controllers. This register is available in LPC2134/6/8 devices only.
Table 165: A/D Global Start Register (ADGSR - address 0xE003 4008) bit description
Bit Symbol Value Description
15:0 -
16 BURST 1
0
23:17 -
User manual
Description
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
When DONE is 1, this field contains a binary fraction representing the voltage on
the Ain pin selected by the SEL field, divided by the voltage on the V
the field indicates that the voltage on the Ain pin was less than, equal to, or close to
that on V , while 0x3FF indicates that the voltage on Ain was close to, equal to, or
SSA
greater than that on V
REF
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
These bits contain the channel from which the LS bits were converted (e.g. 000
identifies channel 0, 001 channel 1...).
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
This bit is 1 in burst mode if the results of one or more conversions was (were) lost
and overwritten before the conversion that produced the result in the LS bits. In
non-FIFO operation, this bit is cleared by reading this register.
This bit is set to 1 when an A/D conversion completes. It is cleared when this
register is read and when the ADCR is written. If the ADCR is written while a
conversion is still in progress, this bit is set and a new conversion is started.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
The AD converters do repeated conversions at the rate selected by their CLKS fields,
scanning (if necessary) through the pins selected by 1s in their SEL field. The first
conversion after the start corresponds to the least-significant 1 in the SEL field, then
higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by
clearing this bit, but the conversion that's in progress when this bit is cleared will be
completed.
Important: START bits must be 000 when BURST = 1 or conversons will not start.
Conversions are software controlled and require 11 clocks.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Rev. 01 — 24 June 2005
.
UM10120
Chapter 16: A/D Converter
Reset
value
NA
NA
pin. Zero in
DDA
NA
NA
NA
0
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Reset
value
NA
0
NA
196