Philips LPC213 Series User Manual page 267

Philips Semiconductors
Volume 1
12.2.3 General information . . . . . . . . . . . . . . . . . . . 149
12.2.4 Master operation. . . . . . . . . . . . . . . . . . . . . . 149
12.2.5 Slave operation . . . . . . . . . . . . . . . . . . . . . . . 150
12.2.6 Exception conditions. . . . . . . . . . . . . . . . . . . 150
12.2.7 Read Overrun . . . . . . . . . . . . . . . . . . . . . . . . 150
12.2.8 Write Collision. . . . . . . . . . . . . . . . . . . . . . . . 150
12.2.9 Mode Fault . . . . . . . . . . . . . . . . . . . . . . . . . . 151
12.2.10 Slave Abort . . . . . . . . . . . . . . . . . . . . . . . . . . 151
12.3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 151
12.4 Register description . . . . . . . . . . . . . . . . . . . 151
Chapter 13: SSP Controller (SPI1)
13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
13.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
13.3 Bus description . . . . . . . . . . . . . . . . . . . . . . . 157
13.3.1 Texas Instruments Synchronous Serial (SSI)
frame format . . . . . . . . . . . . . . . . . . . . . . . . . 157
13.3.2 SPI frame format. . . . . . . . . . . . . . . . . . . . . . 158
13.3.3 Clock Polarity (CPOL) and Clock Phase (CPHA)
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
13.3.4 SPI format with CPOL=0,CPHA=0 . . . . . . . . 159
13.3.5 SPI format with CPOL=0,CPHA=1 . . . . . . . . 160
13.3.6 SPI format with CPOL = 1,CPHA = 0 . . . . . . 161
13.3.7 SPI format with CPOL = 1,CPHA = 1 . . . . . . 162
13.3.8 Semiconductor Microwire frame format . . . . 162
13.3.9 Setup and hold time requirements on CS with
respect to SK in Microwire mode . . . . . . . . . 164
13.4 Register description . . . . . . . . . . . . . . . . . . . 164
Chapter 14: Timer/Counter TIMER0 and TIMER1
14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
14.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 170
14.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
14.4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 170
14.5 Register description . . . . . . . . . . . . . . . . . . . 171
14.5.1 Interrupt Register (IR, TIMER0: T0IR -
0xE000 4000 and TIMER1:
T1IR - 0xE000 8000) . . . . . . . . . . . . . . . . . . 173
14.5.2 Timer Control Register (TCR, TIMER0: T0TCR -
0xE000 4004 and TIMER1: T1TCR -
0xE000 8004) . . . . . . . . . . . . . . . . . . . . . . . . 173
14.5.3 Count Control Register (CTCR, TIMER0:
T0CTCR - 0xE000 4070 and TIMER1: T1TCR -
0xE000 8070) . . . . . . . . . . . . . . . . . . . . . . . . 174
14.5.4 Timer Counter (TC, TIMER0: T0TC -
0xE000 4008 and TIMER1:
T1TC - 0xE000 8008) . . . . . . . . . . . . . . . . . . 175
User manual
12.4.1 SPI Control Register
(S0SPCR - 0xE002 0000) . . . . . . . . . . . . . . 152
12.4.2 SPI Status Register
(S0SPSR - 0xE002 0004) . . . . . . . . . . . . . . 153
12.4.3 SPI Data Register (S0SPDR - 0xE002 0008) 154
12.4.4 SPI Clock Counter Register (S0SPCCR -
0xE002 000C) . . . . . . . . . . . . . . . . . . . . . . . 154
12.4.5 SPI Interrupt register
(S0SPINT - 0xE002 001C). . . . . . . . . . . . . . 154
12.5 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 155
13.4.1 SSP Control Register 0
(SSPCR0 - 0xE006 8000) . . . . . . . . . . . . . . 165
13.4.2 SSP Control Register 1
(SSPCR1 - 0xE006 8004) . . . . . . . . . . . . . . 166
13.4.3 SSP Data Register (SSPDR - 0xE006 8008) 167
13.4.4 SSP Status Register
(SSPSR - 0xE006 800C) . . . . . . . . . . . . . . . 167
13.4.5 SSP Clock Prescale Register (SSPCPSR -
0xE006 8010). . . . . . . . . . . . . . . . . . . . . . . . 167
13.4.6 SSP Interrupt Mask Set/Clear register (SSPIMSC
- 0xE006 8014) . . . . . . . . . . . . . . . . . . . . . . 168
13.4.7 SSP Raw Interrupt Status register (SSPRIS -
0xE006 8018). . . . . . . . . . . . . . . . . . . . . . . . 168
13.4.8 SSP Masked Interrupt register (SSPMIS -
0xE006 801C) . . . . . . . . . . . . . . . . . . . . . . . 169
13.4.9 SSP Interrupt Clear Register (SSPICR -
0xE006 8020). . . . . . . . . . . . . . . . . . . . . . . . 169
14.5.5 Prescale Register (PR, TIMER0: T0PR -
0xE000 400C and TIMER1:
T1PR - 0xE000 800C) . . . . . . . . . . . . . . . . . 175
14.5.6 Prescale Counter Register (PC, TIMER0: T0PC -
0xE000 4010 and TIMER1:
T1PC - 0xE000 8010) . . . . . . . . . . . . . . . . . 175
14.5.7 Match Registers (MR0 - MR3) . . . . . . . . . . . 175
14.5.8 Match Control Register (MCR, TIMER0: T0MCR -
0xE000 4014 and TIMER1: T1MCR -
0xE000 8014). . . . . . . . . . . . . . . . . . . . . . . . 176
14.5.9 Capture Registers (CR0 - CR3) . . . . . . . . . . 177
14.5.10 Capture Control Register (CCR, TIMER0: T0CCR
- 0xE000 4028 and TIMER1: T1CCR -
0xE000 8028). . . . . . . . . . . . . . . . . . . . . . . . 177
14.5.11 External Match Register (EMR, TIMER0: T0EMR
- 0xE000 403C; and TIMER1: T1EMR -
0xE000 803C) . . . . . . . . . . . . . . . . . . . . . . . 178
Rev. 01 — 24 June 2005
UM10120
Chapter 24: Supplementary information
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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