Power Control For Peripherals Register (Pconp - 0Xe01F Coc4) - Philips LPC213 Series User Manual

Philips Semiconductors
Volume 1
Table 23:
Bit
0
1
2
7:3
[1]

3.8.3 Power Control for Peripherals register (PCONP - 0xE01F COC4)

The PCONP register allows turning off selected peripheral functions for the purpose of
saving power. This is accomplished by gating off the clock source to the specified
peripheral blocks. A few peripheral functions cannot be turned off (i.e. the Watchdog timer,
GPIO, the Pin Connect block, and the System Control block). Some peripherals,
particularly those that include analog functions, may consume power that is not clock
dependent. These peripherals may contain a separate disable control that turns off
additional circuitry to reduce power. Each bit in PCONP controls one of the peripherals.
The bit numbers correspond to the related peripheral number as shown in the VPB
peripheral map
Addressing" chapter.
If a peripheral control bit is 1, that peripheral is enabled. If a peripheral bit is 0, that
peripheral is disabled to conserve power. For example if bit 19 is 1, the I
enabled. If bit 19 is 0, the I
Important: valid read from a peripheral register and valid write to a peripheral
register is possible only if that peripheral is enabled in the PCONP register!
User manual
Power Control register (PCON - address 0xE01F COCO) bit description
Symbol Description
IDL Idle mode - when 1, this bit causes the processor clock to be stopped,
while on-chip peripherals remain active. Any enabled interrupt from a
peripheral or an external interrupt source will cause the processor to
resume execution.
PD Power-down mode - when 1, this bit causes the oscillator and all
on-chip clocks to be stopped. A wakeup condition from an external
interrupt can cause the oscillator to restart, the PD bit to be cleared,
and the processor to resume execution.
PDBOD When PD is 1 and this bit is 0, Brown Out Detection remains operative
during Power-down mode, such that its Reset can release the
microcontroller from Power-down mode
both 1, the BOD circuit is disabled during Power-down mode to
conserve power. When PD is 0, the state of this bit has no effect.
- Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Since execution is delayed until after the Wakeup Timer has allowed the main oscillator to resume stable
operation, there is no guarantee that execution will resume before V
threshhold, which prevents execution. If execution does resume, there is no guarantee of how long the
microcontroller will continue execution before the lower BOD threshhold terminates execution. These issues
depend on the slope of the decline of V
vicinity of the microcontroller will improve the likelihood that software will be able to do what needs to be
done when power is being lost.
Figure 5 "VPB peripheral map"
2
C1 interface is disabled.
Rev. 01 — 24 June 2005
Chapter 3: System Control Block
[1]
. When PD and this bit are
DD
. High decoupling capacitance (between V
DD
in the "LPC2131/2/4/6/8 Memory
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
UM10120
Reset
value
0
0
0
NA
has fallen below the lower BOD
and ground) in the
DD
2
C1 interface is
34