Philips LPC213 Series User Manual page 167

Philips Semiconductors
Volume 1
13.4.3 SSP Data Register (SSPDR - 0xE006 8008)
Software can write data to be transmitted to this register, and read data that has been
received.
Table 137: SSP Data Register (SSPDR - address 0xE006 8008) bit description
Bit
15:0
13.4.4 SSP Status Register (SSPSR - 0xE006 800C)
This read-only register reflects the current status of the SSP controller.
Table 138: SSP Status Register (SSPDR - address 0xE006 800C) bit description
Bit
0
1
2
3
4
7:5
13.4.5 SSP Clock Prescale Register (SSPCPSR - 0xE006 8010)
This register controls the factor by which the Prescaler divides the VPB clock PCLK to
yield the prescaler clock that is, in turn, divided by the SCR factor in SSPCR0, to
determine the bit clock.
Table 139: SSP Clock Prescale Register (SSPCPSR - address 0xE006 8010) bit description
Bit
7:0
User manual
Symbol Description
DATA Write: software can write data to be sent in a future frame to this
register whenever the TNF bit in the Status register is 1,
indicating that the Tx FIFO is not full. If the Tx FIFO was
previously empty and the SSP controller is not busy on the bus,
transmission of the data will begin immediately. Otherwise the
data written to this register will be sent as soon as all previous
data has been sent (and received). If the data length is less than
16 bits, software must right-justify the data written to this register.
Read: software can read data from this register whenever the
RNE bit in the Status register is 1, indicating that the Rx FIFO is
not empty. When software reads this register, the SSP controller
returns data from the least recent frame in the Rx FIFO. If the
data length is less than 16 bits, the data is right-justified in this
field with higher order bits filled with 0s.
Symbol Description
TFE Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty,
0 if not.
TNF Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 1
RNE Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is
empty, 1 if not.
RFF Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if
not.
BSY Busy. This bit is 0 if the SSP controller is idle, or 1 if it is
currently sending/receiving a frame and/or the Tx FIFO is not
empty.
- Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Symbol Description
CPSDVSR This even value between 2 and 254, by which PCLK is divided
to yield the prescaler output clock. Bit 0 always reads as 0.
Rev. 01 — 24 June 2005
UM10120
Chapter 13: SSP
Reset value
0x0000
Reset value
1
0
0
0
NA
Reset value
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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