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Philips Semiconductors
Volume 1
24.4 Tables
Table 1:
LPC2131/2132/2134/2136/2138 device
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 2:
ARM exception vector locations . . . . . . . . . . . .12
Table 3:
LPC2131/2/4/6/8 memory mapping modes . . .12
Table 4:
Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 5:
Summary of system control registers . . . . . . . .17
Table 6:
Recommended values for C
mode (crystal and external components
parameters) . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 7:
External interrupt registers . . . . . . . . . . . . . . . .20
Table 8:
External Interrupt Flag register (EXTINT - address
0xE01F C140) bit description . . . . . . . . . . . . . .21
Table 9:
Interrupt Wakeup register (INTWAKE - address
0xE01F C144) bit description . . . . . . . . . . . . . .22
Table 10: External Interrupt Mode register (EXTMODE -
address 0xE01F C148) bit description . . . . . . .23
Table 11: External Interrupt Polarity register (EXTPOLAR -
address 0xE01F C14C) bit description. . . . . . .23
Table 12: Memory Mapping control register (MEMMAP -
address 0xE01F C040) bit description . . . . . . .26
Table 13: PLL registers . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 14: PLL Control register (PLLCON - address
0xE01F C080) bit description . . . . . . . . . . . . . .29
Table 15: PLL Configuration register (PLLCFG - address
0xE01F C084) bit description . . . . . . . . . . . . . .29
Table 16: PLL Status register (PLLSTAT - address
0xE01F C088) bit description . . . . . . . . . . . . . .30
Table 17: PLL Control bit combinations . . . . . . . . . . . . . .30
Table 18: PLL Feed register (PLLFEED - address
0xE01F C08C) bit description. . . . . . . . . . . . . .31
Table 19: Elemens determining PLL's frequency . . . . . . .31
Table 20: PLL Divider values . . . . . . . . . . . . . . . . . . . . . .32
Table 21: PLL Multiplier values. . . . . . . . . . . . . . . . . . . . .32
Table 22: Power control registers . . . . . . . . . . . . . . . . . . .33
Table 23: Power Control register (PCON - address
0xE01F COCO) bit description . . . . . . . . . . . . .34
Table 24: Power Control for Peripherals register (PCONP -
address 0xE01F C0C4) bit description. . . . . . .35
Table 25: Reset Source identificator Register (RSIR -
address 0xE01F C180) bit description . . . . . . .37
Table 26: VPB divider register map . . . . . . . . . . . . . . . . .38
Table 27: VPB Divider register (VPBDIV - address
0xE01F C100) bit description . . . . . . . . . . . . . .39
Table 28: MAM Responses to program accesses of various
types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Table 29: MAM responses to data and DMA accesses of
various types. . . . . . . . . . . . . . . . . . . . . . . . . . .45
Table 30: Summary of MAM registers . . . . . . . . . . . . . . .46
User manual
Table 31: MAM Control Register (MAMCR - address
Table 32: MAM Timing register (MAMTIM - address
Table 33: VIC register map . . . . . . . . . . . . . . . . . . . . . . . 49
Table 34: Software Interrupt register (VICSoftInt - address
in oscillation
X1/X2
Table 35: Software Interrupt register (VICSoftInt - address
Table 36: Software Interrupt Clear register (VICSoftIntClear
Table 37: Software Interrupt Clear register (VICSoftIntClear
Table 38: Raw Interrupt status register (VICRawIntr -
Table 39: Raw Interrupt status register (VICRawIntr -
Table 40: Interrupt Enable register (VICIntEnable - address
Table 41: Interrupt Enable register (VICIntEnable - address
Table 42: Software Interrupt Clear register (VICIntEnClear -
Table 43: Software Interrupt Clear register (VICIntEnClear -
Table 44: Interrupt Select register (VICIntSelect - address
Table 45: Interrupt Select register (VICIntSelect - address
Table 46: IRQ Status register (VICIRQStatus - address
Table 47: IRQ Status register (VICIRQStatus - address
Table 48: FIQ Status register (VICFIQStatus - address
Table 49: FIQ Status register (VICFIQStatus - address
Table 50: Vector Control registers 0-15 (VICvectCntl0-15 -
Table 51: Vector Address registers (VICVectAddr0-15 -
Table 52: Default Vector Address register (VICDefVectAddr
Table 53: Vector Address register (VICVectAddr - address
Table 54: Protection Enable register (VICProtection -
Table 55: Connection of interrupt sources to the Vectored
Rev. 01 — 24 June 2005
Chapter 24: Supplementary information
0xE01F C000) bit description. . . . . . . . . . . . . . 46
0xE01F C004) bit description. . . . . . . . . . . . . . 46
0xFFFF F018) bit allocation . . . . . . . . . . . . . . 50
0xFFFF F018) bit description. . . . . . . . . . . . . . 51
- address 0xFFFF F01C) bit allocation . . . . . . 51
- address 0xFFFF F01C) bit description . . . . . 51
address 0xFFFF F008) bit allocation . . . . . . . 52
address 0xFFFF F008) bit description . . . . . . . 52
0xFFFF F010) bit allocation . . . . . . . . . . . . . . 52
0xFFFF F010) bit description. . . . . . . . . . . . . . 53
address 0xFFFF F014) bit allocation . . . . . . . 53
address 0xFFFF F014) bit description . . . . . . . 53
0xFFFF F00C) bit allocation . . . . . . . . . . . . . . 53
0xFFFF F00C) bit description . . . . . . . . . . . . . 54
0xFFFF F000) bit allocation . . . . . . . . . . . . . . 54
0xFFFF F000) bit description. . . . . . . . . . . . . . 54
0xFFFF F004) bit allocation . . . . . . . . . . . . . . 55
0xFFFF F004) bit description. . . . . . . . . . . . . . 55
0xFFFF F200-23C) bit description . . . . . . . . . . 55
addresses 0xFFFF F100-13C) bit description . 56
- address 0xFFFF F034) bit description. . . . . . 56
0xFFFF F030) bit description. . . . . . . . . . . . . . 56
address 0xFFFF F020) bit description . . . . . . . 56
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
UM10120
continued >>
257
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