Philips LPC213 Series User Manual page 54

Philips Semiconductors
Volume 1
Bit 23
Symbol -
Access R/W
Bit 15
Symbol EINT1
Access R/W
Bit 7
Symbol UART1
Access R/W
Table 45: Interrupt Select register (VICIntSelect - address 0xFFFF F00C) bit description
Bit Symbol
31:0 See
VICIntSelect
bit allocation
table.
5.4.7 IRQ Status register (VICIRQStatus - 0xFFFF F000)
This is a read only register. This register reads out the state of those interrupt requests
that are enabled and classified as IRQ. It does not differentiate between vectored and
non-vectored IRQs.
Table 46: IRQ Status register (VICIRQStatus - address 0xFFFF F000) bit allocation
Reset value: 0x0000 0000
Bit 31
Symbol -
Access RO
Bit 23
Symbol -
Access RO
Bit 15
Symbol EINT1
Access RO
Bit 7
Symbol UART1
Access RO
Table 47: IRQ Status register (VICIRQStatus - address 0xFFFF F000) bit description
Bit Symbol
31:0 See
VICIRQStatus
bit allocation
table.
User manual
22 21
- AD1
R/W R/W
14 13
EINT0 RTC
R/W R/W
6 5
UART0 TIMER1
R/W R/W
Value Description
0 The interrupt request with this bit number is assigned to the IRQ
category.
1 The interrupt request with this bit number is assigned to the FIQ
category.
30 29
- -
RO RO
22 21
- AD1
RO RO
14 13
EINT0 RTC
RO RO
6 5
UART0 TIMER1
RO RO
Description
A bit read as 1 indicates a coresponding interrupt request being enabled,
classified as IRQ, and asserted
Rev. 01 — 24 June 2005
20 19
BOD I2C1
R/W R/W
12 11
PLL SPI1/SSP
R/W R/W
4 3
TIMER0 ARMCore1
R/W R/W
28 27
- -
RO RO
20 19
BOD I2C1
RO RO
12 11
PLL SPI1/SSP
RO RO
4 3
TIMER0 ARMCore1
RO RO
UM10120
Chapter 5: VIC
18 17
AD0 EINT3
R/W R/W
10 9
SPI0 I2C0
R/W R/W
2 1
ARMCore0 -
R/W R/W
26 25
- -
RO RO
18 17
AD0 EINT3
RO RO
10 9
SPI0 I2C0
RO RO
2 1
ARMCore0 -
RO RO
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
16
EINT2
R/W
8
PWM0
R/W
0
WDT
R/W
Reset
value
0
24
-
RO
16
EINT2
RO
8
PWM0
RO
0
WDT
RO
Reset
value
0
54