Pll Control Register (Pllcon - 0Xe01F C080) - Philips LPC213 Series User Manual

Philips Semiconductors
Volume 1
PLLC
Direct
0
PSEL[1:0]
PD
PLLE
Bypass
0
F
OSC
PLOCK
MSEL[4:0]
Fig 10. PLL block diagram

3.7.2 PLL Control register (PLLCON - 0xE01F C080)

The PLLCON register contains the bits that enable and connect the PLL. Enabling the
PLL allows it to attempt to lock to the current settings of the multiplier and divider values.
Connecting the PLL causes the processor and all chip functions to run from the PLL
output clock. Changes to the PLLCON register do not take effect until a correct PLL feed
sequence has been given (see
0xE01F C08C)"
on page
User manual
PHASE-
FREQUENCY
CCO
DETECTOR
PD
CD
F
OUT
DIV-BY-M
MSEL<4:0>
and Section 3.7.3 "PLL Configuration register (PLLCFG - 0xE01F C084)"
29).
Rev. 01 — 24 June 2005
Chapter 3: System Control Block
CLOCK
SYNCHRONIZATION
PD
1
CD
F
CCO
0
/2P
Section 3.7.7 "PLL Feed register (PLLFEED -
UM10120
0
0 CCLK
1
1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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