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Philips Semiconductors
Volume 1
Table 16:
Bit
4:0
6:5
7
8
9
10
15:11
3.7.5 PLL Interrupt
The PLOCK bit in the PLLSTAT register is connected to the interrupt controller. This allows
for software to turn on the PLL and continue with other functions without having to wait for
the PLL to achieve lock. When the interrupt occurs (PLOCK = 1), the PLL may be
connected, and the interrupt disabled.
3.7.6 PLL Modes
The combinations of PLLE and PLLC are shown in
Table 17:
PLLC
0
0
1
1
3.7.7 PLL Feed register (PLLFEED - 0xE01F C08C)
A correct feed sequence must be written to the PLLFEED register in order for changes to
the PLLCON and PLLCFG registers to take effect. The feed sequence is:
User manual
PLL Status register (PLLSTAT - address 0xE01F C088) bit description
Symbol
Description
MSEL
Read-back for the PLL Multiplier value. This is the value currently
used by the PLL.
PSEL
Read-back for the PLL Divider value. This is the value currently
used by the PLL.
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
PLLE
Read-back for the PLL Enable bit. When one, the PLL is currently
activated. When zero, the PLL is turned off. This bit is automatically
cleared when Power-down mode is activated.
PLLC
Read-back for the PLL Connect bit. When PLLC and PLLE are both
one, the PLL is connected as the clock source for the
microcontroller. When either PLLC or PLLE is zero, the PLL is
bypassed and the oscillator clock is used directly by the
microcontroller. This bit is automatically cleared when Power-down
mode is activated.
PLOCK
Reflects the PLL Lock status. When zero, the PLL is not locked.
When one, the PLL is locked onto the requested frequency.
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
PLL Control bit combinations
PLLE
PLL Function
0
PLL is turned off and disconnected. The system runs from the unmodified clock
input.
1
The PLL is active, but not yet connected. The PLL can be connected after
PLOCK is asserted.
0
Same as 00 combination. This prevents the possibility of the PLL being
connected without also being enabled.
1
The PLL is active and has been connected as the system clock source.
1. Write the value 0xAA to PLLFEED.
2. Write the value 0x55 to PLLFEED.
Rev. 01 — 24 June 2005
UM10120
Chapter 3: System Control Block
Table
17.
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Reset
value
0
0
NA
0
0
0
NA
30
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