Philips LPC213 Series User Manual page 118

Philips Semiconductors
Volume 1
The contents of the I
will set bits in the I
Conversely, writing to I2CONCLR will clear bits in the I
to ones in the value written.
11.6.9 Status decoder and Status register
The status decoder takes all of the internal status bits and compresses them into a 5-bit
code. This code is unique for each I
generate vector addresses for fast processing of the various service routines. Each
service routine processes a particular bus status. There are 26 possible bus states if all
four modes of the I
significant bits of the status register when the serial interrupt flag is set (by hardware) and
remains stable until the interrupt flag is cleared by software. The three least significant bits
of the status register are always zero. If the status code is used as a vector to service
routines, then the routines are displaced by eight address locations. Eight bytes of code is
sufficient for most of the service routines (see the software example in this section).
11.7 Register description
Each I
2
Table 107: I C register map
Name Description
2
I2CONSET I C Control Set Register. When a one is written to a bit
of this register, the corresponding bit in the I
register is set. Writing a zero has no effect on the
corresponding bit in the I
2
I2STAT I C Status Register. During I
provides detailed status codes that allow software to
determine the next action needed.
2
I2DAT I C Data Register. During master or slave transmit mode,
data to be transmitted is written to this register. During
master or slave receive mode, data that has been
received may be read from this register.
2
I2ADR I C Slave Address Register. Contains the 7-bit slave
address for operation of the I
and is not used in master mode. The least significant bit
determines whether a slave responds to the general call
address.
I2SCLH SCH Duty Cycle Register High Half Word. Determines
the high time of the I
I2SCLL SCL Duty Cycle Register Low Half Word. Determines
the low time of the I
together determine the clock frequency generated by an
2
I C master and certain times used in slave mode.
2
I2CONCLR I C Control Clear Register. When a one is written to a
bit of this register, the corresponding bit in the I
register is cleared. Writing a zero has no effect on the
corresponding bit in the I
[1]
User manual
2
C control register may be read as I2CONSET. Writing to I2CONSET
2
C control register that correspond to ones in the value written.
2
C block are used. The 5-bit status code is latched into the five most
2
C interface contains 7 registers as shown in
2
C control register.
2
C operation, this register
2
C interface in slave mode,
2
C clock.
2
C clock. I2nSCLL and I2nSCLH
2
C control register.
Reset value relects the data stored in used bits only. It does not include reserved bits content.
Rev. 01 — 24 June 2005
2
C-bus status. The 5-bit code may be used to
Table 107
Access Reset
value
R/W 0x00
2
C control
RO 0xF8
R/W 0x00
R/W 0x00
R/W 0x04
R/W 0x04
WO NA
2
C control
UM10120
2
Chapter 11: I C interfaces
2
C control register that correspond
below.
2 2
I C0 Address I C1 Address
[1]
and Name and Name
0xE001 C000 0xE005 C000
I2C0CONSET I2C1CONSET
0xE001 C004 0xE005 C004
I2C0STAT I2C1STAT
0xE001 C008 0xE005 C008
I2C0DAT I2C1DAT
0xE001 C00C 0xE005 C00C
I2C0ADR I2C1ADR
0xE001 C010 0xE005 C010
I2C0SCLH I2C1SCLH
0xE001 C014 0xE005 C014
I2C0SCLL I2C1SCLL
0xE001 C018 0xE005 C018
I2C0CONCLR I2C1CONCLR
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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