Philips LPC213 Series User Manual page 90

Philips Semiconductors
Volume 1
The UART0 THRE interrupt (U0IIR[3:1] = 001) is a third level interrupt and is activated
when the UART0 THR FIFO is empty provided certain initialization conditions have been
met. These initialization conditions are intended to give the UART0 THR FIFO a chance to
fill up with data to eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit whenever
THRE=1 and there have not been at least two characters in the U0THR at one time since
the last THRE = 1 event. This delay is provided to give the CPU time to write data to
U0THR without a THRE interrupt to decode and service. A THRE interrupt is set
immediately if the UART0 THR FIFO has held two or more characters at one time and
currently, the U0THR is empty. The THRE interrupt is reset when a U0THR write occurs or
a read of the U0IIR occurs and the THRE is the highest interrupt (U0IIR[3:1] = 001).
9.3.7 UART0 FIFO Control Register (U0FCR - 0xE000 C008)
The U0FCR controls the operation of the UART0 Rx and TX FIFOs.
Table 82:
Bit
0
1
2
5:3
7:6
9.3.8 UART0 Line Control Register (U0LCR - 0xE000 C00C)
The U0LCR determines the format of the data character that is to be transmitted or
received.
User manual
UART0 FIFO Control Register (U0FCR - address 0xE000 C008) bit description
Symbol Value Description
FIFO Enable 0 UART0 FIFOs are disabled. Must not be used in the
application.
1 Active high enable for both UART0 Rx and TX
FIFOs and U0FCR[7:1] access. This bit must be set
for proper UART0 operation. Any transition on this
bit will automatically clear the UART0 FIFOs.
RX FIFO 0 No impact on either of UART0 FIFOs.
Reset
1 Writing a logic 1 to U0FCR[1] will clear all bytes in
UART0 Rx FIFO and reset the pointer logic. This bit
is self-clearing.
TX FIFO 0 No impact on either of UART0 FIFOs.
Reset
1 Writing a logic 1 to U0FCR[2] will clear all bytes in
UART0 TX FIFO and reset the pointer logic. This bit
is self-clearing.
- 0 Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is
not defined.
RX Trigger These two bits determine how many receiver
Level UART0 FIFO characters must be written before an
00 interrupt is activated.
Trigger level 0 (1 character or 0x01)
01 Trigger level 1 (4 characters or 0x04)
10 Trigger level 2 (8 characters or 0x08)
11 Trigger level 3 (14 characters or 0x0E)
Rev. 01 — 24 June 2005
UM10120
Chapter 9: UART0
Reset value
0
0
0
NA
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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