Philips LPC213 Series User Manual page 150

Philips Semiconductors
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Note that a read or write of the SPI data register is required in order to clear the SPIF
status bit. Therefore, if the optional read of the SPI data register does not take place, a
write to this register is required in order to clear the SPIF status bit.
12.2.5 Slave operation
The following sequence describes how one should process a data transfer with the SPI
block when it is set up to be a slave. This process assumes that any prior data transfer has
already completed. It is required that the system clock driving the SPI logic be at least 8X
faster than the SPI.
Note that a read or write of the SPI data register is required in order to clear the SPIF
status bit. Therefore, at least one of the optional reads or writes of the SPI data register
must take place, in order to clear the SPIF status bit.
12.2.6 Exception conditions
12.2.7 Read Overrun
A read overrun occurs when the SPI block internal read buffer contains data that has not
been read by the processor, and a new transfer has completed. The read buffer containing
valid data is indicated by the SPIF bit in the status register being active. When a transfer
completes, the SPI block needs to move the received data to the read buffer. If the SPIF
bit is active (the read buffer is full), the new receive data will be lost, and the read overrun
(ROVR) bit in the status register will be activated.
12.2.8 Write Collision
As stated previously, there is no write buffer between the SPI block bus interface, and the
internal shift register. As a result, data must not be written to the SPI data register when a
SPI data transfer is currently in progress. The time frame where data cannot be written to
the SPI data register is from when the transfer starts, until after the status register has
been read when the SPIF status is active. If the SPI data register is written in this time
frame, the write data will be lost, and the write collision (WCOL) bit in the status register
will be activated.
User manual
1. Set the SPI control register to the desired settings.
2. Write the data to transmitted to the SPI data register (optional). Note that this can only
be done when a slave SPI transfer is not in progress.
3. Wait for the SPIF bit in the SPI status register to be set to 1. The SPIF bit will be set
after the last sampling clock edge of the SPI data transfer.
4. Read the SPI status register.
5. Read the received data from the SPI data register (optional).
6. Go to step 2 if more data is required to transmit.
Rev. 01 — 24 June 2005
UM10120
Chapter 12: SPI
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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