Philips LPC213 Series User Manual page 259

Philips Semiconductors
Volume 1
configure Master mode . . . . . . . . . . . . . . . . . .111
Table 106:I2C0CONSET and I2C1CONSET used to
configure Slave mode . . . . . . . . . . . . . . . . . . .112
2
Table 107:I C register map . . . . . . . . . . . . . . . . . . . . . . .118
2
Table 108:I C Control Set register (I2CONSET: I2C0,
I2C0CONSET - address 0xE001 C000 and I2C1,
I2C1CONSET - address 0xE005 C000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .119
2
Table 109:I C Control Set register (I2CONCLR: I2C0,
I2C0CONCLR - address 0xE001 C018 and I2C1,
I2C1CONCLR - address 0xE005 C018) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .120
2
Table 110:I C Status register (I2STAT: I2C0, I2C0STAT -
address 0xE001 C004 and I2C1, I2C1STAT -
address 0xE005 C004) bit description . . . . . .121
2
Table 111:I C Data register ( I2DAT: I2C0, I2C0DAT -
address 0xE001 C008 and I2C1, I2C1DAT -
address 0xE005 C008) bit description . . . . . .121
2
Table 112:I C Slave Address register (I2ADR: I2C0,
I2C0ADR - address 0xE001 C00C and I2C1,
I2C1ADR - address 0xE005 C00C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .122
2
Table 113:I C SCL High Duty Cycle register (I2SCLH: I2C0,
I2C0SCLH - address 0xE001 C010 and I2C1,
I2C1SCLH - address 0xE005 C010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .122
2
Table 114:I C SCL Low Duty Cycle register (I2SCLL: I2C0,
I2C0SCLL - address 0xE001 C014 and I2C1,
I2C1SCLL - address 0xE005 C014) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .122
2
Table 115:Example I C clock rates . . . . . . . . . . . . . . . . .123
Table 116:Abbreviations used to describe an I
operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Table 117:I2CONSET used to initialize Master Transmitter
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Table 118:I2C0ADR and I2C1ADR usage in Slave Receiver
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Table 119:I2C0CONSET and I2C1CONSET used to initialize
Slave Receiver mode . . . . . . . . . . . . . . . . . . .125
Table 120:Master Transmitter mode . . . . . . . . . . . . . . . .130
Table 121:Master Receiver mode . . . . . . . . . . . . . . . . . .131
Table 122:Slave Receiver mode . . . . . . . . . . . . . . . . . . .132
Table 123:Slave Transmitter mode . . . . . . . . . . . . . . . . .134
Table 124:Miscellaneous States . . . . . . . . . . . . . . . . . . .136
Table 125:SPI data to clock phase relationship. . . . . . . .148
Table 126:SPI pin description . . . . . . . . . . . . . . . . . . . . .151
Table 127:SPI register map . . . . . . . . . . . . . . . . . . . . . . .152
Table 128:SPI Control Register (S0SPCR - address
0xE002 0000) bit description . . . . . . . . . . . . .152
Table 129:SPI Status Register (S0SPSR - address
0xE002 0004) bit description . . . . . . . . . . . . .153
User manual
Table 130:SPI Data Register (S0SPDR - address
Table 131:SPI Clock Counter Register (S0SPCCR - address
Table 132:SPI Interrupt register (S0SPINT - address
Table 133:SSP pin descriptions . . . . . . . . . . . . . . . . . . . 156
Table 134:SSP register map. . . . . . . . . . . . . . . . . . . . . . 165
Table 135:SSP Control Register 0 (SSPCR0 - address
Table 136:SSP Control Register 1 (SSPCR1 - address
Table 137:SSP Data Register (SSPDR - address
Table 138:SSP Status Register (SSPDR - address
Table 139:SSP Clock Prescale Register (SSPCPSR -
Table 140:SSP Interrupt Mask Set/Clear register (SSPIMSC
Table 141:SSP Raw Interrupt Status register (SSPRIS -
Table 142:SSP Masked Interrupt Status register (SSPMIS
Table 143:SSP interrupt Clear Register (SSPICR - address
Table 144:Timer/Counter pin description . . . . . . . . . . . . 171
Table 145:TIMER/COUNTER0 and TIMER/COUNTER1
Table 146:Interrupt Register (IR, TIMER0: T0IR - address
2
C
Table 147:Timer Control Register (TCR, TIMER0: T0TCR -
Table 148:Count Control Register (CTCR, TIMER0:
Table 149:Match Control Register (MCR, TIMER0: T0MCR -
Table 150:Capture Control Register (CCR, TIMER0: T0CCR
Table 151:External Match Register (EMR, TIMER0: T0EMR
Table 152:External match control . . . . . . . . . . . . . . . . . . 179
Table 153:Set and reset inputs for PWM Flip-Flops . . . . 184
Table 154:Pin summary . . . . . . . . . . . . . . . . . . . . . . . . . 185
Rev. 01 — 24 June 2005
Chapter 24: Supplementary information
0xE002 0008) bit description . . . . . . . . . . . . . 154
0xE002 000C) bit description. . . . . . . . . . . . . 154
0xE002 001C) bit description. . . . . . . . . . . . . 155
0xE006 8000) bit description . . . . . . . . . . . . . 165
0xE006 8004) bit description . . . . . . . . . . . . . 166
0xE006 8008) bit description . . . . . . . . . . . . . 167
0xE006 800C) bit description. . . . . . . . . . . . . 167
address 0xE006 8010) bit description . . . . . . 167
- address 0xE006 8014) bit description . . . . . 168
address 0xE006 8018) bit description . . . . . . 168
-address 0xE006 801C) bit description . . . . . 169
0xE006 8020) bit description . . . . . . . . . . . . . 169
register map . . . . . . . . . . . . . . . . . . . . . . . . . . 172
0xE000 4000 and TIMER1: T1IR - address
0xE000 8000) bit description . . . . . . . . . . . . . 173
address 0xE000 4004 and TIMER1: T1TCR -
address 0xE000 8004) bit description . . . . . . 174
T0CTCR - address 0xE000 4070 and TIMER1:
T1TCR - address 0xE000 8070) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
address 0xE000 4014 and TIMER1: T1MCR -
address 0xE000 8014) bit description . . . . . . 176
- address 0xE000 4028 and TIMER1: T1CCR -
address 0xE000 8028) bit description . . . . . . 177
- address 0xE000 403C and TIMER1: T1EMR -
address0xE000 803C) bit description . . . . . . 178
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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