Philips LPC213 Series User Manual page 192

Philips Semiconductors
Volume 1
The order of writing the two PWM Match registers is not important, since neither value will
be used until after the write to PWMLER. This insures that both values go into effect at the
same time, if that is required. A single value may be altered in the same way if needed.
The function of each of the bits in the PWMLER is shown in
Table 160: PWM Latch Enable Register (PWMLER - address 0xE001 4050) bit description
Bit
0
1
2
3
4
5
6
7
User manual
Symbol Description
Enable PWM Writing a one to this bit allows the last value written to the PWM
Match 0 Latch Match 0 register to be become effective when the timer is next
reset by a PWM Match event. See
Control Register (PWMMCR - 0xE001
Enable PWM Writing a one to this bit allows the last value written to the PWM
Match 1 Latch Match 1 register to be become effective when the timer is next
reset by a PWM Match event. See
Control Register (PWMMCR - 0xE001
Enable PWM Writing a one to this bit allows the last value written to the PWM
Match 2 Latch Match 2 register to be become effective when the timer is next
reset by a PWM Match event. See
Control Register (PWMMCR - 0xE001
Enable PWM Writing a one to this bit allows the last value written to the PWM
Match 3 Latch Match 3 register to be become effective when the timer is next
reset by a PWM Match event. See
Control Register (PWMMCR - 0xE001
Enable PWM Writing a one to this bit allows the last value written to the PWM
Match 4 Latch Match 4 register to be become effective when the timer is next
reset by a PWM Match event. See
Control Register (PWMMCR - 0xE001
Enable PWM Writing a one to this bit allows the last value written to the PWM
Match 5 Latch Match 5 register to be become effective when the timer is next
reset by a PWM Match event. See
Control Register (PWMMCR - 0xE001
Enable PWM Writing a one to this bit allows the last value written to the PWM
Match 6 Latch Match 6 register to be become effective when the timer is next
reset by a PWM Match event. See
Control Register (PWMMCR - 0xE001
- Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Rev. 01 — 24 June 2005
UM10120
Chapter 15: PWM
Table 160.
Section 15.4.7 "PWM Match
4014)".
Section 15.4.7 "PWM Match
4014)".
Section 15.4.7 "PWM Match
4014)".
Section 15.4.7 "PWM Match
4014)".
Section 15.4.7 "PWM Match
4014)".
Section 15.4.7 "PWM Match
4014)".
Section 15.4.7 "PWM Match
4014)".
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Reset
value
0
0
0
0
0
0
0
NA
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