Philips LPC213 Series User Manual page 213

Philips Semiconductors
Volume 1
19.4 Register description
The watchdog contains 4 registers as shown in
Table 186: Watchdog register map
Name
WDMOD
WDTC
WDFEED Watchdog Feed sequence register. Writing 0xAA
WDTV
[1]
19.4.1 Watchdog Mode register (WDMOD - 0xE000 0000)
The WDMOD register controls the operation of the watchdog as per the combination of
WDEN and RESET bits.
Table 187: Watchdog operating modes selection
WDEN
0
1
1
Once the WDEN and/or WDRESET bits are set they can not be cleared by software. Both
flags are cleared by an external reset or a watchdog timer underflow.
WDTOF The Watchdog Time-Out Flag is set when the watchdog times out. This flag is
cleared by software.
WDINT The Watchdog Interrupt Flag is set when the watchdog times out. This flag is
cleared when any reset occurs. Once the watchdog interrupt is serviced, it can be
disabled in the VIC or the watchdog interrupt request will be generated indefinitely.
User manual
Description
Watchdog Mode register. This register contains
the basic mode and status of the Watchdog Timer.
Watchdog Timer Constant register. This register
determines the time-out value.
followed by 0x55 to this register reloads the
Watchdog timer to its preset value.
Watchdog Timer Value register. This register reads
out the current value of the Watchdog timer.
Reset value relects the data stored in used bits only. It does not include reserved bits content.
WDRESET Mode of Operation
X (0 or 1) Debug/Operate without the watchdog running.
0 Watchdog Interrupt Mode: debug with the Watchdog interrupt but no
WDRESET enabled.
When this mode is selected, a watchdog counter underflow will set the
WDINT flag and the watchdog interrupt request will be generated.
1 Watchdog Reset Mode: operate with the watchdog interrupt and
WDRESET enabled.
When this mode is selected, a watchdog counter underflow will reset
the microcontroller. While the watchdog interrupt is also enabled in
this case (WDEN = 1) it will not be recognized since the watchdog
reset will clear the WDINT flag.
Rev. 01 — 24 June 2005
UM10120
Table 186 below.
Access Reset
value
R/W 0
R/W 0xFF
WO NA
RO 0xFF
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Chapter 19: WDT
Address
[1]
0xE000 0000
0xE000 0004
0xE000 0008
0xE000 000C
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