Table of Contents
Advertisement
Philips Semiconductors
Volume 1
3.9.1 Reset Source Identification Register (RSIR - 0xE01F C180)
This register contains one bit for each source of Reset. Writing a 1 to any of these bits
clears the corresponding read-side bit to 0. The interactions among the four sources are
described below.
Table 25:
Bit
0
1
User manual
External
reset
Watchdog
reset
Power
down
EINT0 Wakeup
EINT1 Wakeup
EINT2 Wakeup
EINT3 Wakeup
RTC Wakeup
Fig 11. Reset block diagram including the wakeup timer
Reset Source identificator Register (RSIR - address 0xE01F C180) bit description
Symbol Description
POR
Assertion of the POR signal sets this bit, and clears all of the other bits
in this register. But if another Reset signal (e.g., External Reset) remains
asserted after the POR signal is negated, then its bit is set. This bit is not
affected by any of the other sources of Reset.
EXTR
Assertion of the RESET signal sets this bit. Ths bit is cleared by POR,
but is not affected by WDT or BOD reset.
Rev. 01 — 24 June 2005
Chapter 3: System Control Block
C
Q
S
WAKEUP TIMER
START
Oscillator
output
(F
)
OSC
Write "1"
from VPB
Reset
UM10120
Reset to the
on-chip
circuitry
Reset to
PCON.PD
COUNT 2
n
C
Q
S
VBP Read
of PDBIT
in PCON
F
OSC
to PLL
Reset
value
see text
see text
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
37
Advertisement
Table of Contents
