Philips LPC213 Series User Manual page 209

Philips Semiconductors
Volume 1
PREINT = int (PCLK / 32768) − 1 = 304 and
PREFRAC = PCLK − ([PREINT + 1] × 32768) = 5,760.
In this case, 5,760 of the prescaler output clocks will be 306 (305 + 1) PCLKs long, the
rest will be 305 PCLKs long.
In a similar manner, any PCLK rate greater than 65.536 kHz (as long as it is an even
number of cycles per second) may be turned into a 32 kHz reference clock for the RTC.
The only caveat is that if PREFRAC does not contain a zero, then not all of the 32,768 per
second clocks are of the same length. Some of the clocks are one PCLK longer than
others. While the longer pulses are distributed as evenly as possible among the remaining
pulses, this "jitter" could possibly be of concern in an application that wishes to observe
the contents of the Clock Tick Counter (CTC)
Register (CTCR - 0xE002 4004)" on page
18.6.4 Prescaler operation
The Prescaler block labelled "Combination Logic" in
decrement of the 13-bit PREINT counter is extended by one PCLK. In order to both insert
the correct number of longer cycles, and to distribute them evenly, the ombinatorial Logic
associates each bit in PREFRAC with a combination in the 15-bit Fraction Counter. These
associations are shown in the following
User manual
CLK UNDERFLOW
13 BIT INTEGER COUNTER
(DOWN COUNTER)
RELOAD
13
13 BIT RELOAD INTEGER
REGISTER
(PREINT)
13
Fig 52. RTC prescaler block diagram
Rev. 01 — 24 June 2005
directly(Section 18.4.4 "Clock Tick Counter
203).
To clock tick
counter clock
15 BIT FRACTION COUNTER
COMBINATORIAL LOGIC
Extend
reload
15 BIT FRACTION REGISTER
(PREFRAC)
VPB Bus
Figure 52 determines when the
Table 184.
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
UM10120
Chapter 18: RTC
PCLK
(VPB Clock)
CLK
15
15
15
209