Register Description - Philips LPC213 Series User Manual

Philips Semiconductors
Volume 1
The PLL is turned off and bypassed following a chip Reset and when by entering
Power-down mode. The PLL is enabled by software only. The program must configure and
activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source.

3.7.1 Register description

The PLL is controlled by the registers shown in
follow.
Warning: Improper setting of the PLL values may result in incorrect operation of the
device!
Table 13:
Name
PLLCON
PLLCFG
PLLSTAT
PLLFEED
[1]
User manual
PLL registers
Description
PLL Control Register. Holding register for
updating PLL control bits. Values written to this
register do not take effect until a valid PLL feed
sequence has taken place.
PLL Configuration Register. Holding register for
updating PLL configuration values. Values
written to this register do not take effect until a
valid PLL feed sequence has taken place.
PLL Status Register. Read-back register for
PLL control and configuration information. If
PLLCON or PLLCFG have been written to, but
a PLL feed sequence has not yet occurred, they
will not reflect the current PLL state. Reading
this register provides the actual values
controlling the PLL, as well as the status of the
PLL.
PLL Feed Register. This register enables
loading of the PLL control and configuration
information from the PLLCON and PLLCFG
registers into the shadow registers that actually
affect PLL operation.
Reset value relects the data stored in used bits only. It does not include reserved bits content.
Rev. 01 — 24 June 2005
UM10120
Chapter 3: System Control Block
Table 13. More detailed descriptions
Access Reset
value
R/W 0
R/W 0
RO 0
WO NA
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Address
[1]
0xE01F C080
0xE01F C084
0xE01F C088
0xE01F C08C
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