Philips LPC213 Series User Manual page 121

Philips Semiconductors
Volume 1
Table 109: I
Bit Symbol
5
6
7
AAC is the Assert Acknowledge Clear bit. Writing a 1 to this bit clears the AA bit in the
I2CONSET register. Writing 0 has no effect.
SIC is the I
register. Writing 0 has no effect.
STAC is the Start flag Clear bit. Writing a 1 to this bit clears the STA bit in the I2CONSET
register. Writing 0 has no effect.
I2ENC is the I
I2CONSET register. Writing 0 has no effect.
11.7.3 I
I2C1STAT - 0xE005 C004)
Each I
Status register is Read-Only.
Table 110: I
Bit Symbol
2:0 -
7:3 Status
The three least significant bits are always 0. Taken as a byte, the status register contents
represent a status code. There are 26 possible status codes. When the status code is
0xF8, there is no relevant information available and the SI bit is not set. All other 25 status
codes correspond to defined I
be set. For a complete list of status codes, refer to tables from
11.7.4 I
I2C1DAT - 0xE005 C008)
This register contains the data to be transmitted or the data just received. The CPU can
read and write to this register only while it is not in the process of shifting a byte, when the
SI bit is set. Data in I2DAT remains stable as long as the SI bit is set. Data in I2DAT is
always shifted from right to left: the first bit to be transmitted is the MSB (bit 7), and after a
byte has been received, the first bit of received data is located at the MSB of I2DAT.
Table 111: I
Bit Symbol
7:0 Data
User manual
2
C Control Set register (I2CONCLR: I2C0, I2C0CONCLR - address 0xE001 C018
and I2C1, I2C1CONCLR - address 0xE005 C018) bit description
Description
STAC START flag Clear bit.
2
I2ENC I C interface Disable bit.
- Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
2
C Interrupt Clear bit. Writing a 1 to this bit clears the SI bit in the I2CONSET
2
C Interface Disable bit. Writing a 1 to this bit clears the I2EN bit in the
2
C Status register (I2STAT: I2C0, I2C0STAT - 0xE001 C004 and I2C1,
2
C Status register reflects the condition of the corresponding I
2
C Status register (I2STAT: I2C0, I2C0STAT - address 0xE001 C004 and I2C1,
I2C1STAT - address 0xE005 C004) bit description
Description
These bits are unused and are always 0.
These bits give the actual status information about the I
2
C Data register (I2DAT: I2C0, I2C0DAT - 0xE001 C008 and I2C1,
2
C Data register ( I2DAT: I2C0, I2C0DAT - address 0xE001 C008 and I2C1, I2C1DAT
- address 0xE005 C008) bit description
Description
This register holds data values that have been received, or are to
be transmitted.
Rev. 01 — 24 June 2005
2
C states. When any of these states entered, the SI bit will
UM10120
2
Chapter 11: I C interfaces
Reset
value
0
0
NA
2
C interface. The I
Reset value
0
2
C interface. 0x1F
Table 120 to Table 123.
Reset value
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
2
C
121