Power Control Usage Notes; Reset - Philips LPC213 Series User Manual

Philips Semiconductors
Volume 1
Table 24:
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
18:13 -
19
20
31:21 -

3.8.4 Power control usage notes

After every reset, the PCONP register contains the value that enables all interfaces and
peripherals controlled by the PCONP to be enabled. Therefore, apart from proper
configuring via peripheral dedicated registers, the user's application has no need to
access the PCONP in order to start using any of the on-board peripherals.
Power saving oriented systems should have 1s in the PCONP register only in positions
that match peripherals really used in the application. All other bits, declared to be
"Reserved" or dedicated to the peripherals not used in the current application, must be
cleared to 0.

3.9 Reset

Reset has two sources on the LPC2131/2/4/6/8: the RESET pin and Watchdog Reset.
The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of
chip Reset by any source starts the Wakeup Timer (see description in
User manual
Power Control for Peripherals register (PCONP - address 0xE01F C0C4) bit
description
Symbol Description
- Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
PCTIM0 Timer/Counter 0 power/clock control bit.
PCTIM1 Timer/Counter 1 power/clock control bit.
PCUART0 UART0 power/clock control bit.
PCUART1 UART1 power/clock control bit.
PCPWM0 PWM0 power/clock control bit.
- Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
2
PCI2C0 The I C0 interface power/clock control bit.
PCSPI0 The SPI0 interface power/clock control bit.
PCRTC The RTC power/clock control bit.
PCSPI1 The SSP interface power/clock control bit.
- Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
PCAD0 A/D converter 0 (ADC0) power/clock control bit.
Note: Clear the PDN bit in the AD0CR before clearing this bit, and set
this bit before setting PDN.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
2
PCI2C1 The I C1 interface power/clock control bit.
PCAD1 A/D converter 1 (ADC1) power/clock control bit.
Note: Clear the PDN bit in the AD1CR before clearing this bit, and set
this bit before setting PDN.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 01 — 24 June 2005
UM10120
Chapter 3: System Control Block
Section 3.11
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Reset
value
NA
1
1
1
1
1
NA
1
1
1
1
NA
1
NA
1
1
NA
35