Philips LPC213 Series User Manual page 237

21.1 Features
21.2 Applications
The EmbeddedICE logic provides on-chip debug support. The debugging of the target
system requires a host computer running the debugger software and an EmbeddedICE
protocol convertor. EmbeddedICE protocol convertor converts the Remote Debug
Protocol commands to the JTAG data needed to access the ARM7TDMI-S core present
on the target system.
21.3 Description
The ARM7TDMI-S Debug Architecture uses the existing JTAG
accessing the core. The scan chains that are around the core for production test are
reused in the debug state to capture information from the databus and to insert new
information into the core or the memory. There are two JTAG-style scan chains within the
ARM7TDMI-S. A JTAG-style Test Access Port Controller controls the scan chains. In
addition to the scan chains, the debug architecture uses EmbeddedICE logic which
resides on chip with the ARM7TDMI-S core. The EmbeddedICE has its own scan chain
that is used to insert watchpoints and breakpoints for the ARM7TDMI-S core. The
EmbeddedICE logic consists of two real time watchpoint registers, together with a control
and status register. One or both of the watchpoint registers can be programmed to halt the
ARM7TDMI-S core. Execution is halted when a match occurs between the values
programmed into the EmbeddedICE logic and the values currently appearing on the
address bus, databus and some control signals. Any bit can be masked so that its value
does not affect the comparison. Either watchpoint register can be configured as a
watchpoint (i.e. on a data access) or a break point (i.e. on an instruction fetch). The
watchpoints and breakpoints can be combined such that:
1.For more details refer to IEEE Standard 1149.1 - 1990 Standard Test Access Port and Boundary Scan Architecture.
User manual
UM10120
Chapter 21: EmbeddedICE logic
Rev. 01 — 24 June 2005
•
No target resources are required by the software debugger in order to start the
debugging session.
•
Allows the software debugger to talk via a JTAG (Joint Test Action Group) port directly
to the core.
•
Inserts instructions directly in to the ARM7TDMI-S core.
•
The ARM7TDMI-S core or the System state can be examined, saved or changed
depending on the type of instruction inserted.
•
Allows instructions to execute at a slow debug speed or at a fast system speed.
•
The conditions on both watchpoints must be satisfied before the ARM7TDMI core is
stopped. The CHAIN functionality requires two consecutive conditions to be satisfied
before the core is halted. An example of this would be to set the first breakpoint to
Rev. 01 — 24 June 2005
User manual
1
port as a method of
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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