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Philips Semiconductors
Volume 1
Table 27:
Bit
1:0
7:2
3.11 Wakeup timer
The purpose of the wakeup timer is to ensure that the oscillator and other analog
functions required for chip operation are fully functional before the processor is allowed to
execute instructions. This is important at power on, all types of Reset, and whenever any
of the aforementioned functions are turned off for any reason. Since the oscillator and
other functions are turned off during Power-down mode, any wakeup of the processor
from Power-down mode makes use of the Wakeup Timer.
The Wakeup Timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of V
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.
Once a clock is detected, the Wakeup Timer counts 4096 clocks, then enables the on-chip
circuitry to initialize. When the onboard modules initialization is complete, the processor is
released to execute instructions if the external Reset has been deasserted. In the case
where an external clock source is used in the system (as opposed to a crystal connected
to the oscillator pins), the possibility that there could be little or no delay for oscillator
start-up must be considered. The Wakeup Timer design then ensures that any other
required chip functions will be operational prior to the beginning of program execution.
User manual
VPB Divider register (VPBDIV - address 0xE01F C100) bit description
Symbol Value
VPBDIV 00
01
10
11
-
-
Crystal oscillator
or
external clock source
(F
)
OSC
Fig 12. VPB divider connections
Rev. 01 — 24 June 2005
Description
VPB bus clock is one fourth of the processor clock.
VPB bus clock is the same as the processor clock.
VPB bus clock is one half of the processor clock.
Reserved. If this value is written to the VPBDIV register, it
has no effect (the previous setting is retained).
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
PLL
ramp (in the case of power on), the type of crystal
DD
UM10120
Chapter 3: System Control Block
Processor clock
(CCLK)
VPB
VPB Clock
DIVIDER
(PCLK)
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Reset
value
00
NA
39
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