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Philips Semiconductors
Volume 1
11.8.3 Slave Receiver mode
In the slave receiver mode, a number of data bytes are received from a master transmitter
(see
follows:
Table 118: I2C0ADR and I2C1ADR usage in Slave Receiver mode
The upper 7 bits are the address to which the I
master. If the LSB (GC) is set, the I
(0x00); otherwise it ignores the general call address.
Table 119: I2C0CONSET and I2C1CONSET used to initialize Slave Receiver mode
The I
to logic 1 to enable the I
acknowledge its own slave address or the general call address. STA, STO, and SI must be
reset.
When I2ADR and I2CON have been initialized, the I
its own slave address followed by the data direction bit which must be "0" (W) for the I
block to operate in the slave receiver mode. After its own slave address and the W bit have
been received, the serial interrupt flag (SI) is set and a valid status code can be read from
I2STAT. This status code is used to vector to a state service routine. The appropriate
action to be taken for each of these status codes is detailed in Table 104. The slave
receiver mode may also be entered if arbitration is lost while the I
mode (see status 0x68 and 0x78).
If the AA bit is reset during a transfer, the I
to SDA after the next received data byte. While AA is reset, the I
to its own slave address or a general call address. However, the I
and address recognition may be resumed at any time by setting AA. This means that the
AA bit may be used to temporarily isolate the I
User manual
Figure
31). To initiate the slave receiver mode, I2ADR and I2CON must be loaded as
Bit
7
6
Symbol
Bit
7
6
Symbol
-
I2EN
Value
-
1
2
C-bus rate settings do not affect the I
2
Rev. 01 — 24 June 2005
5
4
own slave 7-bit address
2
C block will respond when addressed by a
2
C block will respond to the general call address
5
4
STA
STO
0
0
2
C block in the slave mode. I2EN must be set
C block. The AA bit must be set to enable the I
2
C block will return a not acknowledge (logic 1)
2
C block from the I
UM10120
Chapter 11: I
3
2
1
3
2
1
SI
AA
-
0
1
-
2
C block to
2
C block waits until it is addressed by
2
C block is in the master
2
C block does not respond
2
C-bus is still monitored
2
C-bus.
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
2
C interfaces
0
GC
0
-
-
2
C
125
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