Pll And Power-Down Mode; Pll Frequency Calculation - Philips LPC213 Series User Manual

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The two writes must be in the correct sequence, and must be consecutive VPB bus
cycles. The latter requirement implies that interrupts must be disabled for the duration of
the PLL feed operation. If either of the feed values is incorrect, or one of the previously
mentioned conditions is not met, any changes to the PLLCON or PLLCFG register will not
become effective.
Table 18:
Bit
7:0

3.7.8 PLL and Power-down mode

Power-down mode automatically turns off and disconnects the PLL. Wakeup from
Power-down mode does not automatically restore the PLL settings, this must be done in
software. Typically, a routine to activate the PLL, wait for lock, and then connect the PLL
can be called at the beginning of any interrupt service routine that might be called due to
the wakeup. It is important not to attempt to restart the PLL by simply feeding it when
execution resumes after a wakeup from Power-down mode. This would enable and
connect the PLL at the same time, before PLL lock is established.

3.7.9 PLL frequency calculation

The PLL equations use the following parameters:
Table 19:
Element
F
F
CCLK
M
P
The PLL output frequency (when the PLL is both active and connected) is given by:
CCLK = M × F
The CCO frequency can be computed as:
F
The PLL inputs and settings must meet the following:
User manual
PLL Feed register (PLLFEED - address 0xE01F C08C) bit description
Symbol Description
PLLFEED The PLL feed sequence must be written to this register in order for
PLL configuration and control register changes to take effect.
Elemens determining PLL's frequency
Description
the frequency from the crystal oscillator/external osicillator
OSC
the frequency of the PLL current controlled oscillator
CCO
the PLL output frequency (also the processor clock frequency)
PLL Multiplier value from the MSEL bits in the PLLCFG register
PLL Divider value from the PSEL bits in the PLLCFG register
or CCLK = F
OSC
= CCLK × 2 × P or F
CCO
•
F is in the range of 10 MHz to 25 MHz.
OSC
•
CCLK is in the range of 10 MHz to F
microcontroller - determined by the system microcontroller is embedded in).
•
F is in the range of 156 MHz to 320 MHz.
CCO
Rev. 01 — 24 June 2005
/ (2 × P)
CCO
× M × 2 × P
= F
CCO OSC
(the maximum allowed frequency for the
max
UM10120
Chapter 3: System Control Block
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Reset
value
0x00
31