Philips LPC213 Series User Manual page 109

11.1 Features
11.2 Applications
Interfaces to external I
etc.
11.3 Description
A typical I
direction bit (R/W), two types of data transfers are possible on the I
The LPC2131/2/4/6/8 I
master transmitter mode, master receiver mode, slave transmitter mode and slave
receiver mode.
The I
power off to the LPC2131/2/4/6/8 without causing a problem with other devices on the
same I
"Fast-Mode", and notes for the table titled "Characteristics of the SDA and SCL I/O stages
User manual
UM10120
2
Chapter 11: I C interfaces I
Rev. 01 — 24 June 2005
• 2
Standard I C compliant bus interfaces that may be configured as Master, Slave, or
Master/Slave.
•
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
•
Programmable clock to allow adjustment of I
•
Bidirectional data transfer between masters and slaves.
•
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
•
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• 2
The I C-bus may be used for test and diagnostic purposes.
2
C standard parts, such as serial RAMs, LCDs, tone generators,
2
C-bus configuration is shown in
•
Data transfer from a master transmitter to a slave receiver. The first byte transmitted
by the master is the slave address. Next follows a number of data bytes. The slave
returns an acknowledge bit after each received byte.
•
Data transfer from a slave transmitter to a master receiver. The first byte (the slave
address) is transmitted by the master. The slave then returns an acknowledge bit.
Next follows the data bytes transmitted by the slave to the master. The master returns
an acknowledge bit after all received bytes other than the last byte. At the end of the
last received byte, a "not acknowledge" is returned. The master device generates all
of the serial clock pulses and the START and STOP conditions. A transfer is ended
with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the I
released.
2
C interfaces are byte oriented, and have four operating modes:
2
C interfaces complie with entire I
2
C-bus (see "The I
Rev. 01 — 24 June 2005
2
C0 and I
2
Figure
2
C specification, supporting the ability to turn
2
C-bus specification" description under the heading
2
C1
User manual
C transfer rates.
20. Depending on the state of the
2
C-bus:
2
C-bus will not be
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
109