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Philips Semiconductors
Volume 1
Table 11:
Bit Symbol
3
7:4 -
3.5.6 Multiple external interrupt pins
Software can select multiple pins for each of EINT3:0 in the Pin Select registers, which are
described in chapter Pin Connect Block on page 73. The external interrupt logic for each
of EINT3:0 receives the state of all of its associated pins from the pins' receivers, along
with signals that indicate whether each pin is selected for the EINT function. The external
interrupt logic handles the case when more than one pin is so selected, differently
according to the state of its Mode and Polarity bits:
The signal derived by this logic is the EINTi signal in the following logic schematic
Figure
For example, if the EINT3 function is selected in the PINSEL0 and PINSEL1 registers for
pins P0.9, P0.20 and P0.30, and EINT3 is configured to be low level sensitive, the inputs
from all three pins will be logically ANDed. When more than one EINT pin is logically
ORed, the interrupt service routine can read the states of the pins from the GPIO port
using the IO0PIN and IO1PIN registers, to determine which pin(s) caused the interrupt.
User manual
External Interrupt Polarity register (EXTPOLAR - address 0xE01F C14C) bit
description
Value
EXTPOLAR3 0
1
-
•
In Low-Active Level Sensitive mode, the states of all pins selected for the same EINTx
functionality are digitally combined using a positive logic AND gate.
•
In High-Active Level Sensitive mode, the states of all pins selected for the same
EINTx functionality are digitally combined using a positive logic OR gate.
•
In Edge Sensitive mode, regardless of polarity, the pin with the lowest GPIO port
number is used. (Selecting multiple pins for an EINTx in edge-sensitive mode could
be considered a programming error.)
9.
Rev. 01 — 24 June 2005
Description
EINT3 is low-active or falling-edge sensitive (depending on
EXTMODE3).
EINT3 is high-active or rising-edge sensitive (depending on
EXTMODE3).
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
UM10120
Chapter 3: System Control Block
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Reset
value
0
NA
24
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