Philips LPC213 Series User Manual page 194

Philips Semiconductors
Volume 1
16.4 Register description
The A/D Converter registers are shown in
Table 162: ADC registers
Generic Description
Name
ADCR A/D Control Register. The ADCR register must be written
to select the operating mode before A/D conversion can
occur.
ADDR A/D Data Register. This register contains the ADC's
DONE bit and (when DONE is 1) the 10-bit result of the
conversion.
ADGSR A/D Global Start Register. This address can be written (in
the AD0 address range) to start conversions in both A/D
converters simultaneously.
[1]
16.4.1 A/D Control Register (AD0CR - 0xE003 4000 and AD1CR -
0xE006 0000)
Table 163: A/D Control Register (AD0CR - address 0xE003 4000 and AD1CR - address 0xE006 0000) bit description
Bit Symbol Value Description
7:0 SEL
15:8 CLKDIV
16 BURST 1
0
User manual
Reset value relects the data stored in used bits only. It does not include reserved bits content.
Selects which of the AD0.7:0/AD1.7:0 pins is (are) to be sampled and converted. For
AD0, bit 0 selects Pin AD0.0, and bit 7 selects pin AD0.7. In software-controlled mode,
only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8
ones. All zeroes is equivalent to 0x01.
The VPB clock (PCLK) is divided by (this value plus one) to produce the clock for the
A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should
program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but
in certain cases (such as a high-impedance analog source) a slower clock may be
desirable.
The AD converter does repeated conversions at the rate selected by the CLKS field,
scanning (if necessary) through the pins selected by 1s in the SEL field. The first
conversion after the start corresponds to the least-significant 1 in the SEL field, then
higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by
clearing this bit, but the conversion that's in progress when this bit is cleared will be
completed.
Important: START bits must be 000 when BURST = 1 or conversons will not start.
Conversions are software controlled and require 11 clocks.
Rev. 01 — 24 June 2005
Chapter 16: A/D Converter
Table 162.
Access Reset AD0
[1]
value Address
& Name
R/W 0x0000 0001 0xE003 4000
AD0CR
R/W undefined 0xE003 4004
AD0DR
WO 0x00
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
UM10120
AD1
Address
& Name
0xE006 0000
AD1CR
0xE006 0004
AD1DR
0xE003 4008
ADGSR
Reset
value
0x01
0
0
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