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Philips Semiconductors
ARM-based Microcontroller
RESET
Reset has two sources on the LPC2119/2129/2194/2292/2294: the RESET pin and Watchdog Reset. The RESET pin is a
Schmitt trigger input pin with an additional glitch filter. Assertion of chip Reset by any source starts the Wakeup Timer (see
Wakeup Timer description later in this chapter), causing reset to remain asserted until the external Reset is de-asserted, the
oscillator is running, a fixed number of clocks have passed, and the Flash controller has completed its initialization. The
relationship between Reset, the oscillator, and the Wakeup Timer are shown in Figure 16.
The Reset glitch filter allows the processor to ignore external reset pulses that are very short, and also determines the minimum
duration of RESET that must be asserted in order to guarantee a chip reset. Once asserted, RESET pin can be deasserted only
when crystal oscillator is fully running and an adequate signal is present on the X1 pin of the LPC2119/2129/2194/2292/2294.
Assuming that an external crystal is used in the crystal oscillator subsystem, after power on, the RESET pin should be asserted
for 10 ms. For all subsequent resets when crystal osillator is already running and stable signal is on the X1 pin, the RESET pin
needs to be asserted for 300 ns only.
Speaking in general, there are no sequence requirements for powering up the supplies (V
proper reset handling It is absolutely necessary to have valid voltage supply on V
dedicated hardware are powered by them. V
Consequently, not providing V
communicating with external world.
When the internal Reset is removed, the processor begins executing at address 0, which isinitially the Reset vector mapped from
the Boot Block. At that point, all of the processor and peripheral registers have been initialized to predetermined values.
External and internal Resets have some small differences. An external Reset causes the value of certain pins to be latched to
configure the part. External circuitry cannot determine when an internal Reset occurs in order to allow setting up those special
pins, so those latches are not reloaded during an internal Reset. Pins that are examined during an external Reset for various
purposes are: P1.20/TRACESYNC, P1.26/RTCK, BOOT1 and BOOT0 (see chapters Pin Configuration on page 110, Pin
Connect Block on page 126 and External Memory Controller (EMC) on page 56). Pin P0.14 (see Flash Memory System and
Programming on page 262) is exemined by on-chip bootloader when this code is executed after reset.
It is possible for a chip Reset to occur during a Flash programming or erase operation. The Flash memory will interrupt the
ongoing operation and hold off the completion of Reset to the CPU until internal Flash high voltages have settled.
External
Reset
Watchdog
Reset
Power Down
EINT0 Wakeup
EINT1 Wakeup
EINT2 Wakeup
EINT3 Wakeup
CAN1 Wakeup
CAN2 Wakeup
CAN3 Wakeup*
CAN4 Wakeup*
*LPC2194/2292/2294 only
System Control Block
pins enable microcontroller's interface to the environment via its digital pins.
3
power supply will not affect the reset sequence itself, but will prevent microcontroller from
3
C
Q
S
Oscillator
Output (F
OSC
Figure 16: Reset Block Diagram including Wakeup Timer
LPC2119/2129/2194/2292/2294
pins, since on-chip Reset circuit and oscillator
18
Reset to
kFlash shell
Reset to
PCON.PD
Wakeup Timer
n
Start
Count 2
)
Write "1"
from VPB
Reset
85
Preliminary User Manual
, V
, V
and V
). However, for
18
3
18A
3A
C
VPB Read
of PDbit
Q
in PCON
S
F
OSC
PLL
May 03, 2004
to
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