Apb Divider; Register Description; Apbdiv Register (Apbdiv - 0Xe01F C100) - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1

3.11 APB divider

The APB Divider determines the relationship between the processor clock (CCLK) and the
clock used by peripheral devices (PCLK). The APB Divider serves two purposes.
The first is to provides peripherals with desired PCLK via APB bus so that they can
operate at the speed chosen for the ARM processor. In order to achieve this, the APB bus
may be slowed down to one half or one fourth of the processor clock rate. Because the
APB bus must work properly at power up (and its timing cannot be altered if it does not
work since the APB divider control registers reside on the APB bus), the default condition
at reset is for the APB bus to run at one quarter speed.
The second purpose of the APB Divider is to allow power savings when an application
does not require any peripherals to run at the full processor rate.
The connection of the APB Divider relative to the oscillator and the processor clock is
shown in
remains active (if it was running) during Idle mode.

3.11.1 Register description

Only one register is used to control the APB Divider.
Table 28:
Name
APBDIV
[1]

3.11.2 APBDIV register (APBDIV - 0xE01F C100)

The APB Divider register contains two bits, allowing three divider values, as shown in
Table
Table 29:
Bit
1:0
7:2
User manual
Figure 11. Because the APB Divider is connected to the PLL output, the PLL
APB divider register map
Description
Controls the rate of the APB clock in relation to
the processor clock.
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
29.
APB Divider register (APBDIV - address 0xE01F C100) bit description
Symbol Value Description
APBDIV 00 APB bus clock is one fourth of the processor clock.
01 APB bus clock is the same as the processor clock.
10 APB bus clock is one half of the processor clock.
11 Reserved. If this value is written to the APBDIV register, it
has no effect (the previous setting is retained).
- - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 01 — 12 January 2006
UM10161
Chapter 3: System control block
Access Reset Address
[1]
value
R/W 0x00 0xE01F C100
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Reset
value
00
NA
36