Serial Clock Generator; Timing And Control; User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
The synchronization logic will synchronize the serial clock generator with the clock pulses
on the SCL line from another device. If two or more master devices generate clock pulses,
the "mark" duration is determined by the device that generates the shortest "marks," and
the "space" duration is determined by the device that generates the longest "spaces".
Figure 31
A slave may stretch the space duration to slow down the bus master. The space duration
may also be stretched for handshaking purposes. This can be done after each bit or after
a complete byte transfer. the I
been transmitted or received and the acknowledge bit has been transferred. The serial
interrupt flag (SI) is set, and the stretching continues until the serial interrupt flag is
cleared.

11.6.6 Serial clock generator

This programmable clock pulse generator provides the SCL clock pulses when the I
block is in the master transmitter or master receiver mode. It is switched off when the I
block is in a slave mode. The I
via the I
registers for details. The output clock pulses have a duty cycle as programmed unless the
bus is synchronizing with other SCL clock sources as described above.

11.6.7 Timing and control

The timing and control logic generates the timing and control signals for serial byte
handling. This logic block provides the shift pulses for I2DAT, enables the comparator,
generates and detects start and stop conditions, receives and transmits acknowledge bits,
controls the master and slave modes, contains interrupt request logic, and monitors the
2
I

User manual

shows the synchronization procedure.
SDA Line
SCL Line
(1) Another device pulls the SCL line low before this I
device effectively determines the (shorter) HIGH period.
(2) Another device continues to pull the SCL line low after this I
and released SCL. The I
device effectively determines the (longer) LOW period.
(3) The SCL line is released , and the clock generator begins timing the HIGH time.
Fig 31. Serial clock synchronization
2
C Clock Control Registers. See the description of the I2CSCLL and I2CSCLH
C-bus status.
Rev. 01 — 12 January 2006
(1) (3)
(2)
high low
period period
2
C has timed a complete high time. The other
2
C clock generator is forced to wait until SCL goes HIGH. The other
2
C block will stretch the SCL space duration after a byte has
2
C output clock frequency and duty cycle is programmable
UM10161
Chapter 11: I
(1)
2
C has timed a complete low time
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
2
C interfaces
2
C
2
C
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