Spi Control Register (S0Spcr - 0Xe002 0000); User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
Table 140: SPI register map
Name
S0SPCR
S0SPSR
S0SPDR
S0SPCCR SPI Clock Counter Register. This register
S0SPINT
[1]

12.4.1 SPI Control Register (S0SPCR - 0xE002 0000)

The S0SPCR register controls the operation of the SPI0 as per the configuration bits
setting.
Table 141: SPI Control Register (S0SPCR - address 0xE002 0000) bit description
Bit
1:0
2
3
4
5
6

User manual

Description
SPI Control Register. This register controls the
operation of the SPI.
SPI Status Register. This register shows the
status of the SPI.
SPI Data Register. This bi-directional register
provides the transmit and receive data for the
SPI. Transmit data is provided to the SPI0 by
writing to this register. Data received by the SPI0
can be read from this register.
controls the frequency of a master's SCK0.
SPI Interrupt Flag. This register contains the
interrupt flag for the SPI interface.
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Symbol Value Description
- Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
BitEnable 0 The SPI controller sends and receives 8 bits of data per
transfer.
CPHA Clock phase control determines the relationship between
the data and the clock on SPI transfers, and controls
when a slave transfer is defined as starting and ending.
Data is sampled on the first clock edge of SCK. A transfer
0
starts and ends with activation and deactivation of the
SSEL signal.
1 Data is sampled on the second clock edge of the SCK. A
transfer starts with the first clock edge, and ends with the
last sampling edge when the SSEL signal is active.
CPOL Clock polarity control.
0 SCK is active HIGH.
1 SCK is active LOW.
MSTR Master mode select.
0 The SPI operates in Slave mode.
1 The SPI operates in Master mode.
LSBF LSB First controls which direction each byte is shifted
when transferred.
0 SPI data is transferred MSB (bit 7) first.
1 SPI data is transferred LSB (bit 0) first.
Rev. 01 — 12 January 2006
UM10161
Chapter 12: SPI
Access Reset Address
[1]
value
R/W 0x00 0xE002 0000
RO 0x00 0xE002 0004
R/W 0x00 0xE002 0008
R/W 0x00 0xE002 000C
R/W 0x00 0xE002 001C
Reset
value
NA
0
0
0
0
0
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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