Koninklijke Philips Electronics N.v. 2006. All Rights Reserved - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
The registers in
LPC2101/02/03. All of these registers are located directly on the local bus of the CPU for
the fastest possible read and write timing. An additional feature has been added that
provides byte addressability of all GPIO registers. A mask register allows treating groups
of bits in a single GPIO port separately from other bits on the same port.
User must select whether a GPIO will be accessed via registers that provide enhanced
features or a legacy set of registers (see
register (SCS - 0xE01F C1A0)" on page
registers are controlling the same physical pins, these two port control branches are
mutually exclusive and operate independently. For example, changing a pin's output via a
fast register will not be observable via the corresponding legacy register.
The following text will refer to the legacy GPIO as "the slow" GPIO, while GPIO equipped
with the enhanced features will be referred as "the fast" GPIO.
Table 64:
Generic
Name
IOPIN
IOSET
IODIR
IOCLR
[1]
User manual
Table 65 represent the enhanced GPIO features available on the
GPIO register map (legacy APB accessible registers)
Description
GPIO Port Pin value register. The current
state of the GPIO configured port pins can
always be read from this register,
regardless of pin direction.
GPIO Port Output Set register. This
register controls the state of output pins in
conjunction with the IOCLR register.
Writing ones produces HIGHs at the
corresponding port pins. Writing zeroes
has no effect.
GPIO Port Direction control register. This
register individually controls the direction
of each port pin.
GPIO Port Output Clear register. This
register controls the state of output pins.
Writing ones produces LOW at the
corresponding port pins and clears the
corresponding bits in the IOSET register.
Writing zeroes has no effect.
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Rev. 01 — 12 January 2006
Section 3.6.1 "System Control and Status flags
23). While both of a port's fast and legacy GPIO
Acces Reset value
s
R/W NA
R/W 0x0000 0000
R/W 0x0000 0000
WO 0x0000 0000
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
UM10161
Chapter 8: GPIO
[1]
PORT0
Address &
Name
0xE002 8000
IO0PIN
0xE002 8004
IO0SET
0xE002 8008
IO0DIR
0xE002 800C
IO0CLR
72