Uart0 Fractional Divider Register (U0Fdr - 0Xe000 C028); User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
Table 84:
Bit
7:0
Table 85:
Bit
7:0

9.3.4 UART0 Fractional Divider Register (U0FDR - 0xE000 C028)

The UART0 Fractional Divider Register (U0FDR) controls the clock pre-scaler for the baud
rate generation and can be read and written at user's discretion. This pre-scaler takes the
APB clock and generates an output clock per specified fractional requirements.
Table 86:
Bit
3:0
7:4
31:8 -
This register controls the clock pre-scaler for the baud rate generation. The reset value of
the register keeps the fractional capabilities of UART0 disabled making sure that UART0 is
fully software and hardware compatible with UARTs not equipped with this feature.
UART0 baudrate can be calculated as:
Where PCLK is the peripheral clock, U0DLM and U0DLL are the standard UART0 baud
rate divider registers, and DIVADDVAL and MULVAL are UART0 fractional baudrate
generator specific parameters.
The value of MULVAL and DIVADDVAL should comply to the following conditions:

User manual

UART0 Divisor Latch LSB register (U0DLL - address 0xE000 C000, when
DLAB = 1) bit description
Symbol Description
DLL The UART0 Divisor Latch LSB Register, along with the U0DLM
register, determines the baud rate of the UART0.
UART0 Divisor Latch MSB register (U0DLM - address 0xE000 C004, when
DLAB = 1) bit description
Symbol Description
DLM The UART0 Divisor Latch MSB Register, along with the U0DLL
register, determines the baud rate of the UART0.
UART0 Fractional Divider Register (U0FDR - address 0xE000 C028) bit description
Function Description
DIVADDVAL Baudrate generation pre-scaler divisor value. If this field is 0,
fractional baudrate generator will not impact the UART0
baudrate.
MULVAL Baudrate pre-scaler multiplier value. This field must be greater
or equal 1 for UART0 to operate properly, regardless of
whether the fractional baudrate generator is used or not.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
UART0
baudrate
1. 0 < MULVAL ≤ 15
2. 0 ≤ DIVADDVAL ≤ 15
Rev. 01 — 12 January 2006
= -------------------------------------------------------------------------------------------------------------------------------
× ( ×
16 16 U0DLM + U0DLL
UM10161
Chapter 9: UART0
PCLK
⎛
DivAddVal
) ×
1 +
---------------------------- -
⎝
MulVal
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Reset value
0x01
Reset value
0x00
Reset value
0
1
NA
(1)
⎞
⎠
85