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Philips Semiconductors
Volume 1
The ARM7TDMI-S core has a Debug Communication Channel function in-built. The
debug communication channel allows a program running on the target to communicate
with the host debugger or another separate host without stopping the program flow or
even entering the debug state. The debug communication channel is accessed as a
co-processor 14 by the program running on the ARM7TDMI-S core. The debug
communication channel allows the JTAG port to be used for sending and receiving data
without affecting the normal program flow. The debug communication channel data and
control registers are mapped in to addresses in the EmbeddedICE logic.
20.4 Pin description
Table 236: EmbeddedICE pin description
Pin Name
TMS
TCK
TDI
TDO
TRST
DBGSEL
RTCK
20.5 Reset state of multiplexed pins
On the LPC2101/02/03, the pins TMS, TCK, TDI, TDO, AND TRST are multiplexed with
P0.27 - P0.31. To have them come up as a Debug port, connect a weak bias resistor
(4.7-10 kΩ depending on the external JTAG circuitry) between V
User manual
trigger on an access to a peripheral and the second to trigger on the code segment
that performs the task switching. Therefore when the breakpoints trigger the
information regarding which task has switched out will be ready for examination.
•
The watchpoints can be configured such that a range of addresses are enabled for
the watchpoints to be active. The RANGE function allows the breakpoints to be
combined such that a breakpoint is to occur if an access occurs in the bottom 256
bytes of memory but not in the bottom 32 bytes.
Type
Description
Input
Test Mode Select. The TMS pin selects the next state in the TAP state
machine.
Input
Test Clock. This allows shifting of the data in, on the TMS and TDI pins. It
is a positive edge triggered clock with the TMS and TCK signals that
define the internal state of the device.
Input
Test Data In. This is the serial data input for the shift register.
Output
Test Data Output. This is the serial data output from the shift register.
Data is shifted out of the device on the negative edge of the TCK signal.
Input
Test Reset. The TRST pin can be used to reset the test logic within the
EmbeddedICE logic.
Input
Debug Select. When LOW at Reset, the P0.27 - P0.31 pins are
configured for alternate use via the Pin Connect Block. When HIGH at
Reset, the debug mode is entered.
For functionality provided by DBGSEL, see
on page 252
Output
Returned Test Clock. Extra signal added to the JTAG port. Required for
designs based on ARM7TDMI-S processor core. Multi-ICE (Development
system from ARM) uses this signal to maintain synchronization with
targets having slow or widely varying clock frequency. For details refer to
"Multi-ICE System Design considerations Application Note 72 (ARM DAI
0072A)". Also used during entry into debug mode.
Rev. 01 — 12 January 2006
UM10161
Chapter 20: EmbeddedICE
Section 20.8 "DEBUG mode"
and the RTCK pin. To
SS
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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