Solution 2: Disable Irqs And Fiqs Using Separate Writes To The Cpsr; Solution 3: Re-Enable Fiqs At The Beginning Of The Irq Handler; Vic Usage Notes - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
This code will test for the situation where the IRQ was received during a write to disable
IRQs. If this is the case, the code returns immediately - resulting in the IRQ not being
acknowledged (cleared), and further IRQs being disabled.
Similar code may also be applied to the FIQ handler, in order to resolve the first issue.
This is the recommended workaround, as it overcomes both problems mentioned above.
However, in the case of problem two, it does add several cycles to the maximum length of
time FIQs will be disabled.

5.6.4 Solution 2: disable IRQs and FIQs using separate writes to the CPSR

MRS r0, cpsr
ORR r0, r0, #I_Bit
MSR cpsr_c, r0
ORR r0, r0, #F_Bit
MSR cpsr_c, r0
This is the best workaround where the maximum time for which FIQs are disabled is
critical (it does not increase this time at all). However, it does not solve problem one, and
requires extra instructions at every point where IRQs and FIQs are disabled together.

5.6.5 Solution 3: re-enable FIQs at the beginning of the IRQ handler

As the required state of all bits in the c field of the CPSR are known, this can be most
efficiently be achieved by writing an immediate value to CPSR_C, for example:
MSR cpsr_c, #I_Bit:OR:irq_MODE
This requires only the IRQ handler to be modified, and FIQs may be re-enabled more
quickly than by using workaround 1. However, this should only be used if the system can
guarantee that FIQs are never disabled while IRQs are enabled. It does not address
problem one.

5.7 VIC usage notes

If user code is running from an on-chip RAM and an application uses interrupts, interrupt
vectors must be re-mapped to on-chip address 0x0. This is necessary because all the
exception vectors are located at addresses 0x0 and above. This is easily achieved by
configuring the MEMMAP register (see
(MEMMAP - 0xE01F C040)" on page
linked such that at 0x4000 0000 the Interrupt Vector Table (IVT) will reside.
Although multiple sources can be selected (VICIntSelect) to generate FIQ request, only
one interrupt service routine should be dedicated to service all available/present FIQ
request(s). Therefore, if more than one interrupt sources are classified as FIQ the FIQ
interrupt service routine must read VICFIQStatus to decide based on this content what to
User manual
; are next enabled.
; Rest of interrupt routine
;disable IRQs
;disable FIQs
;IRQ should be disabled
;FIQ enabled
;ARM state, IRQ mode
Section 3.7.1 "Memory Mapping control register
23) to User RAM mode. Application code should be
Rev. 01 — 12 January 2006
UM10161
Chapter 5: VIC
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
57