Uart0 Scratch Pad Register; 0Xe000 C01C); User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
Table 93: UART0 Line Status Register (U0LSR - address 0xE000 C014, read only) bit description
Bit Symbol Value Description
3 Framing Error
(FE)
0
1
4 Break Interrupt
(BI)
0
1
5 Transmitter
Holding
Register Empty
0
(THRE))
1
6 Transmitter
Empty
(TEMT)
0
1
7 Error in RX
FIFO
(RXFE)
0
1
9.3.11 UART0 Scratch Pad Register (U0SCR - 0xE000 C01C)
The U0SCR has no effect on the UART0 operation. This register can be written and/or
read at user's discretion. There is no provision in the interrupt interface that would indicate
to the host that a read or write of the U0SCR has occurred.
Table 94: UART0 Scratch Pad Register (U0SCR - address 0xE000 C01C) bit description
Bit Symbol
7:0 Pad

User manual

When the stop bit of a received character is a logic 0, a framing error occurs.
An U0LSR read clears U0LSR[3]. The time of the framing error detection is
dependent on U0FCR0. Upon detection of a framing error, the Rx will attempt
to resynchronize to the data and assume that the bad stop bit is actually an
early start bit. However, it cannot be assumed that the next received byte will
be correct even if there is no Framing Error.
Note: A framing error is associated with the character at the top of the UART0
RBR FIFO.
Framing error status is inactive.
Framing error status is active.
When RXD0 is held in the spacing state (all 0's) for one full character
transmission (start, data, parity, stop), a break interrupt occurs. Once the
break condition has been detected, the receiver goes idle until RXD0 goes to
marking state (all 1's). An U0LSR read clears this status bit. The time of break
detection is dependent on U0FCR[0].
Note: The break interrupt is associated with the character at the top of the
UART0 RBR FIFO.
Break interrupt status is inactive.
Break interrupt status is active.
THRE is set immediately upon detection of an empty UART0 THR and is
cleared on a U0THR write.
U0THR contains valid data.
U0THR is empty.
TEMT is set when both U0THR and U0TSR are empty; TEMT is cleared when
either the U0TSR or the U0THR contain valid data.
U0THR and/or the U0TSR contains valid data.
U0THR and the U0TSR are empty.
U0LSR[7] is set when a character with a Rx error such as framing error, parity
error or break interrupt, is loaded into the U0RBR. This bit is cleared when the
U0LSR register is read and there are no subsequent errors in the UART0
FIFO.
U0RBR contains no UART0 RX errors or U0FCR[0]=0.
UART0 RBR contains at least one UART0 RX error.
Description
A readable, writable byte.
Rev. 01 — 12 January 2006
UM10161
Chapter 9: UART0
Reset value
0
0
1
1
0
Reset value
0x00
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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